Methods of fabricating semiconductor devices having a dual...

Details Methods of fabricating semiconductor devices having a dual... Methods of fabricating semiconductor devices having a dual...

2007-11-20

2007-11-20

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S224000, C438S201000, C438S202000, C438S207000, C438S217000, C257S368000, C257S351000, C257S347000, C257S369000, C257SE21632, C257SE21640

Reexamination Certificate

active

11246471

ABSTRACT:
In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

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“Notice to Submit Response,” issued by the Korean Intellectual Property Office on Nov. 24, 2006, corresponding to Korean Patent Application No. 10-2005-113411.

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