Methods of fabricating scaled MOSFETs

Details Methods of fabricating scaled MOSFETs Methods of fabricating scaled MOSFETs

2001-10-25

2002-09-24

Jackson, Jerome (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S305000, C438S592000, C438S595000, C438S596000

Reexamination Certificate

active

06455383

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to metal-oxide-semiconductor field-effect transistors, and more particularly to scaled metal-oxide-semiconductor field-effect transistors (MOSFETs) and their fabrication methods.
2. Description of Related Art
It is well-known that the metal-oxide-semiconductor field-effect transistors (MOSFETs) including an n-channel MOSFET and a p-channel MOSFET in CMOS integrated circuits are scaled down very rapidly, based on the scaling rule in order to gain density *speed-power product. Basically, the surface dimensions of a device including device channel-length and device channel-width can be directly scaled down by using an advanced lithographic technique, and the isolation and contact areas of a device must also be scaled down accordingly in order to increase the packing density of an integrated-circuit. From device physics, the gate-oxide thickness and the source/drain Junction depth are scaled, the lightly-doped drain (LDD) structure is used to reduce the drain-induced barrier lowering (DIBL) and hot-carrier degradation effects, and a deeper channel implant or a pocket (halo) implant using a larger-angle-tilt implantation is used to form the punch-through stop. For a shallow source/drain contact, a barrier-metal layer over a silicided source/drain diffusion region is used. Moreover, the shallow-trench-isolation (STI) instead of the local oxidation of silicon (LOCOS) is used to reduce the isolation area of a device.
Basically, based on the gate structure used in the prior arts, there are polycide-gate land salicide-gate structures.
FIG. 1A
shows a cross-sectional view of a polycide-gate structure in the channel-length direction, in which a tungsten-silicide layer
103
a capping on a doped polycrystalline-silicon layer
102
a
as a gate metal is formed on a thin gate-dielectric layer
101
a
; a masking silicon-nitride layer
104
a
is formed on the tungsten-silicide layer
103
a
and a silicon-nitride spacer
106
a
is formed over the sidewalls of the patterned polycide-gate structure; a lightly-doped source/drain diffusion region
105
a
is formed after patterning the polycide-gate structure and a deeper heavily-doped source/drain diffusion region
107
a
is formed after forming a silicon-nitride spacer
106
a
; a self-aligned silicide layer
108
a
is formed over a deeper heavily-doped source/drain diffusion region
107
a.
FIG. 1B
shows a cross-sectional view of a salicide-gate structure in the channel-length direction, in which a polycrystalline-silicon gate layer
102
a
is formed over a thin gate-dielectric layer
101
a
; a dielectric spacer (oxide)
106
a
is formed over the sidewalls of the patterned gate structure; a lightly-doped source/drain diffusion region
105
a
is formed after patterning the gate structure and a heavily-doped source/drain diffusion region
107
a
is formed after forming a dielectric spacer
106
a
; a self-aligned silicide layer
108
a
,
108
b
is simultaneously formed over the heavily-doped source/drain diffusion region
107
a
and the doped polycrystalline-silicon gate layer
102
a
. Similarly, a silicon-nitride spacer can be used instead of an oxide spacer
106
a
shown in
FIG. 1B
, however, the silicon-nitride spacer being deposited on a thin gate-dielectric layer
101
a
to reduce the stress-induced defects resulting from the silicon-nitride spacer is favorable to eliminate the outdiffusion of boron impurities used to form the lightly-doped source/ drain diffusion region
105
a
for a p-channel MOSFET.
Apparently, as the thin gate-dielectric layer
110
a
is scaled to be thinner than 30 Angstroms, the extension length of the lightly-doped source/drain diffusion region
105
a
shown in FIG.
1
A and
FIG. 1B
becomes a gate leakage path of a scaled MOSFET. Moreover, the overlapping capacitance between the gate and the lightly-doped source/drain diffusion region
105
a
becomes larger, resulting in lower speed performance. In addition, as the gate length is scaled down below 0.25 &mgr;m, the resistance of a narrow gate line becomes higher and the sheet resistance of either polycide gate or salicide gate may also depend on geometries of the gate line due to the agglomeration of the silicide layer, resulting in a higher parasitic resistance for gate interconnection.
FIG.
1
C(
a
) shows a cross-sectional view in the channel-width direction, in which a polycrystalline-silicon gate layer
102
a
is formed over a flat surface formed by the field-oxides (FOX) and the thin-gate dielectric layer
101
a
. It is clearly seen that the trench corners of the semiconductor substrate
100
become the field-emission cathode lines for passing the tunneling current from the channel region to the gate
102
a
. The flat gate layer shown in FIG.
1
C(
a
) is in general good for fine-line lithography of a short-gate length of scaled MOSFETs shown in FIG.
1
A and FIG.
1
B. FIG.
1
C(
b
) shows that a step between the field-oxides (FOX) and the thin gate-dielectric layer
101
a
is formed and a polycrystalline-silicon layer
102
a
is formed over the steps with a non-uniform topography. From FIG.
1
C(
b
), it is clearly seen that the field-emission due to the trench corners can be eliminated, however, a non-uniform topography of the polycrystalline-silicon gate layer is not favorable for fine-line lithography. Moreover, the polycrystalline-silicon gate layer is in general doped by ion-implantation for CMOS fabrication with different doping types for an n-channel MOSFET and a p-channel MOSFET, the non-uniform topography may produce a non-uniform doping depth, resulting in the poly-depletion effect of a scaled MOSFET, especially for a narrow gate-width device.
Based on the above description, there are several issues encountered for a scaled MOSFET. These issues include: (1) high tunneling current between the gate and the source/drain diffusion region through a thin gate-dielectric layer; (2) high parasitic capacitance between the gate and the source/drain diffusion region; (3) high gate-interconnection resistance of a non-planarized conductive gate layer for fine-line lithography; and (4) field-emission through the trench corners of the semiconductor substrate to the gate.
SUMMARY OF THE INVENTION
Accordingly, the present invention discloses scaled MOSFETs and their fabrication methods, in which scaled MOSFETs are formed on a flat shallow-trench-isolation structure. The flat shallow-trench-isolation structure includes an active region having a first conductive gate layer formed over a thin gate-dielectric layer and an isolation region being filled with planarized field-oxides. The first conductive gate layer is made of amorphous-silicon or polycrystalline-silicon and is implanted with doping impurities having a dopant type opposite to that of the semiconductor substrate through a first masking dielectric layer. A thin conductive barrier-metal layer is formed over the flat shallow-trench-isolation structure. The thin conductive barrier-metal layer is preferably a refractory metal-nitride layer such as a titanium-nitride layer. For the first group of scaled MOSFETs, a metal layer is formed over the thin conductive barrier-metal layer and a second masking dielectric layer is formed over the metal layer for forming a composite-gate structure. The metal layer is preferably made of a high melting-point metal such as tungsten. Apparently, the conductive barrier-metal layer is used to prevent the interaction between the first conductive gate layer and the metal layer so that a high-conductivity nature of the metal layer can be maintained. For the second group of scaled MOSFETs, a, second conductive gate layer is formed over the conductive barrier-metal layer for forming a salicide-gate structure and is preferably made of polycrystalline-silicon or amorphous-silicon. Similarly, the conductive barrier-metal layer is used to present the agglomeration of the silicide layer during a self-aligned silicidation of the second conductive gate layer.
For the first group of scaled MOSFETs, a st

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