Methods of fabricating nonvolatile memory devices including...

Details Methods of fabricating nonvolatile memory devices including... Methods of fabricating nonvolatile memory devices including...

2001-05-14

2003-04-08

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000

Reexamination Certificate

active

06544845

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit fabrication, and more particularly to nonvolatile memory devices and methods for fabricating the same.
BACKGROUND OF THE INVENTION
Nonvolatile memory devices are widely used in electronic systems to retain information. One type of nonvolatile memory device is an erasable and programmable read only memory (EPROM). An EPROM is generally electrically programmed by forming channel hot electrons (CHE) in a drain and injecting the channel hot electrons into a floating gate. An erasing operation in the EPROM is generally performed optically by exposing a memory cell to ultraviolet rays and emitting electrons captured by the floating gate.
FIG. 1
is a sectional view of a conventional nonvolatile memory cell in which the programming operation is performed by injecting the CHE formed around the drain from the channel of the drain into the floating gate, as mentioned above.
Referring to
FIG. 1
, in a conventional nonvolatile memory cell, a gate oxide film
102
is formed on an integrated circuit substrate such as a semiconductor substrate
100
and a floating gate
104
is formed thereon. An interlayer dielectric film
106
such as an oxide
itride/oxide (ONO) film is formed on the floating gate
104
and a control gate
108
is formed thereon. Specifically, the floating gate
104
is formed on a channel area between a source region
112
and a drain region
114
. The floating gate
104
is electrically floated and the surroundings thereof are insulated by a silicon oxide film. Therefore, when charges are injected into the floating gate
104
, the charges semi-permanently remain in the floating gate
104
.
FIG. 2
is a circuit diagram partially showing an example of a NOR-type nonvolatile memory device obtained by arranging an array of memory cells shown in FIG.
1
.
The operation of a general nonvolatile memory device is described as follows, referring to
FIGS. 1 and 2
. An operation for reading a selected cell in a circle marked with a reference numeral A is performed by sensing whether there are charges stored in the floating gate
104
. When a voltage Vd, for example, a voltage of 1.0 V is applied to the drain region
114
and a voltage Vcg, for example, a voltage of 1.5 to 5.0 V is applied to the control gate
108
, the existence or nonexistence of drain current flowing from the drain region
114
to the source region
112
is dependent on the quantity of the charges stored in the floating gate
104
. The state of a cell, namely, the on or off state of a transistor, is determined from the existence or nonexistence of the drain current.
A power supply voltage Vcc generally is used as the voltage Vcg which is applied to the control gate
108
. The threshold voltage Vth of the erased cell is preferably low, so that operations can be performed at a wide range of Vcc. Preferably, the threshold voltage of the erased cell is far lower than the power supply voltage applied to the control gate in order to correctly read the information of the erased cell.
CHE injection is used for programming the selected cell in the circle marked with the reference numeral A. When a drain voltage Vd=6 V is applied to a selected bit line (B/L-
1
), a control gate voltage Vcg=10 to 14 V is applied to a selected word line (W/L-
1
), and non-selected word lines (W/L-
2
, W/L-
3
, and W/L-
4
) are all grounded, some of the electrons flowing the channel are accelerated by a lateral electric field by the drain voltage Vd. When the accelerated electrons have sufficient energy for tunneling the gate oxide film
102
of the cell, they are injected into the floating gate
104
by a vertical electric field by the control gate voltage.
Table 1 shows the respective operational conditions of the above-mentioned nonvolatile memory cell array.
TABLE 1
Operation
Program
Read
selected bit line
 6 V
1 V
non-selected bit line
floating
floating or 0 V
selected word line
12 V
Vcc
non-selected word line
 0 V
0 V
common source
 0 V
0 V
semiconductor substrate
 0 V
0 V
The quantity of the electrons captured by the floating gate during the programming operation is generally determined by the electric potential of the floating gate. When the electrons are captured by the floating gate, the threshold voltage Vth of the transistor controlled by the control gate becomes higher. The information “1” or “0” is determined by the change &Dgr;Vth of the threshold voltage.
FIG. 3
is a graph showing the &Dgr;Vth of the threshold voltage after programming and erasing in a nonvolatile memory cell operating as mentioned above.
In general, it is preferable that the threshold voltage is dramatically shifted by a low applied voltage and in a short writing time. Unfortunately however, nonvolatile memory devices may have problems during the programming operation. These problems will be described in detail as follows:
FIG. 4
is an equivalent circuit diagram of the nonvolatile memory cell shown in FIG.
1
. When the programming operation is performed in the NOR-type nonvolatile memory device shown in
FIG. 2
, voltages of 6 V and 0 V are respectively applied to the drain and the control gate of the non-selected cell B that share a bit line with the selected cell A as shown in the Table 1.
Thus, in the non-selected cell B, the floating gate is capacitively coupled to the drain region and the electric potential of the floating gate is affected by the electric potential of the drain region. The floating gate voltage at this time can be expressed as follows:
First, the following Equation 1 can be derived from FIG.
4
:
Vfg=&ggr;cg·Vcg+&ggr;d·Vd+&ggr;s·Vs+&ggr;b·Vb
  (1)
wherein, Vfg is the floating gate voltage, Vcg is the control gate voltage, Vd is the drain voltage, Vs is the source voltage, and Vb is a bulk voltage. Also, &ggr;cg, &ggr;d, &ggr;s and &ggr;b respectively denote coupling ratios and can be represented as follows:
&ggr;cg=Cono/Ctotal
&ggr;d=Cd/Ctotal
&ggr;s=Cs/Ctotal
&ggr;b=Cb/Ctotal
wherein, Ctotal=Cono+Cd+Cb+Cs. Cono is the capacitance of the interlayer dielectric film, Cd is an overlap capacitance between the floating gate and the drain, Cs is an overlap capacitance between the floating gate and the source, and Cb is the capacitance of the gate oxide film.
During the programming operation, the floating gate voltage Vfg is represented by the following Equation 2 since the control gate voltage Vcg, the bulk voltage Vb, and the source voltage Vs of the non-selected cell are all 0 V:
Vfg=&ggr;d·Vd
  (2)
In the cell which is not selected, a weak inversion layer may be formed in the channel area by the voltage induced by the floating gate of the cell due to capacitive coupling. The floating gate voltage may increase and may exceed the threshold voltage Vth in the cell, to thereby completely form the channel. Thus leakage currents through the channel may rapidly increase.
FIG. 5
is a graph showing leakage currents by the drain voltage in the non-selected cell of a conventional NOR-type nonvolatile memory device. The leakage currents generated as mentioned above can cause more serious problems as the threshold voltage Vth of the erased cell becomes lower. Thus, such leakage currents can cause more serious problems to memories which are usable with a wide range of operating voltages Vcc. The leakage currents generated by the drain voltage in the non-selected cell are generated in all the non-selected cells sharing one bit line. Therefore, the voltage applied to the bit line during the programming operation may decrease, thus reducing the programming speed of the selected cell.
In view of the above, it is desirable to prevent the formation of the inversion layer by minimizing the Vfg expressed in the above Equation 2 in order to suppress the leakage currents in the non-selected cell. The capacitive coupling problem and potential solutions to this problem are described in a publication entitled “
Characterization and Suppression of Drai

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