Methods of fabricating multi-gate, offset source and drain field

Details Methods of fabricating multi-gate, offset source and drain field Methods of fabricating multi-gate, offset source and drain field

1997-10-29

1999-03-23

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

438163, 438181, 438195, H01L 2100, H01L 2184, H01L 21338, H01L 21337

Patent

active

058858598

ABSTRACT:
A field effect transistor includes laterally spaced apart source and drain regions in a substrate, laterally spaced apart undoped regions in the substrate between the laterally spaced apart source and drain regions, a doped channel region in the substrate between the laterally spaced apart undoped regions, and a gate insulating layer on the substrate. A main gate is on the gate insulating layer opposite the channel, and first and second sub gates are on the gate insulating layer, a respective one of which is opposite a respective one of the spaced apart undoped regions. The first and second sub gates are laterally spaced apart from and electrically insulated from the main gate. The transistor may be formed by patterning a photoresist layer and a gate layer to form a main gate and first and second sub gates, reflowing the photoresist into the lateral space between the main gate and the first and second sub gates, etching the gate insulating layer using the reflowed photoresist as a mask, and implanting ions into the substrate to form source and drain regions using the etched gate insulating layer as a mask.

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