Methods of fabricating integrated circuit memory devices includi

Details Methods of fabricating integrated circuit memory devices includi Methods of fabricating integrated circuit memory devices includi

1999-05-04

2000-01-18

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438589, H01L 213205

Patent

active

060157488

ABSTRACT:
Integrated circuit memory devices are fabricated by fabricating an array of memory cell field effect transistors and peripheral circuit field effect transistors that are spaced-apart from the memory cell transistors, in an integrated circuit substrate. The memory cell transistors include spaced-apart memory cell transistor source and drain regions and a memory cell gate therebetween. The peripheral circuit transistors include spaced-apart peripheral circuit transistor source and drain regions and a peripheral circuit gate therebetween. A silicide blocking layer is formed on the memory cell transistor source and drain regions. The integrated circuit substrate is silicided to thereby form a silicide layer on the memory cell transistor gates, on the peripheral circuit source and drain regions and on the peripheral circuit gates, such that the memory cell transistor source and drain regions are free of the silicide layer thereon. Accordingly, low contact resistance silicide regions may be selectively provided in memory cells without degrading the leakage characteristics thereof.

REFERENCES:
patent: 5589423 (1994-10-01), White et al.

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