Methods of fabricating integrated circuit memory devices having

Details Methods of fabricating integrated circuit memory devices having Methods of fabricating integrated circuit memory devices having

1998-08-17

2000-09-19

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

438447, 438449, 438451, H01L 2176

Patent

active

06121115&

ABSTRACT:
An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath the first field insulation layer. The first channel stop impurity layer is narrower than the first field insulation area. A second field insulation layer is included in the select transistor area, and a second channel stop impurity layer is included beneath the second field insulation layer. The second channel stop impurity layer is wider than the second field insulation layer. Integrated circuit memory devices are fabricated by defining a memory cell area and a select transistor area of a semiconductor substrate. The memory cell area includes a memory cell active area and a memory cell field area. The select transistor area includes a select transistor active area and a select transistor field area. First channel stop impurity ions are implanted into the select transistor field area. A first field insulation layer is formed in the memory cell field area, and a second field insulation layer is formed in the select transistor field area, such that the first channel stop impurity ions lie beneath the second field insulation area. Second channel stop impurity ions are implanted through the central portion of the first field insulation area, such that the second channel stop impurity ions lie beneath the central portion of the first field insulation layer.

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