Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-01-28
2004-02-10
Le, Dung A (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S259000, C257S321000, C257S315000
Reexamination Certificate
active
06689658
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a stack-gate flash memory array and its fabrication methods, and more particularly, to a high-density and high-performance stack-gate flash memory array and its fabrication methods.
2. Description of Related Art
Basically, flash memory devices can be divided into two categories: a stack-gate structure and a split-gate structure. The stack-gate structure is known to be a one-transistor cell, in which the gate length of a cell can be defined by using the minimum-feature-size of technology used; however, the split-gate structure including a floating gate and a select gate is known to be a 1.5-transistor cell. Therefore, the stack-gate structure is often used in high-density flash memory system.
A typical stack-gate flash memory device is shown in
FIG. 1A
, in which the programming operation is performed by using channel hot-electron injection to inject channel hot-electrons across the barrier height of the thin gate-oxide layer
101
into the floating-gate
102
; the erasing operation is performed by using Fowler-Nordheim tunneling to tunnel stored electrons in the floating-gate
102
through the thin gate-oxide layer
101
into the double-diffused source region
105
a
,
107
a
. The formation of the double-diffused source region is mainly used to offer a larger overlapping area between the floating-gate and the source diffusion region in order to reduce the erasing time and simultaneously to eliminate the band-to-band tunneling effects as a positive voltage is applied to the source for erasing. However, as the stack-gate length is scaled down, the punch-through effect may be easily occurred for a double-diffused structure during the programming operation using channel hot-electron injection. As a consequence, the double-diffused structure becomes an obstacle for device scaling. Moreover, the programming efficiency of the channel hot-electron injection is low and the most part of the channel current is wasted, the programming time becomes longer for a high-density memory system due to the finite loading of the charge-pump circuit.
A stack-gate flash memory device having a symmetrical source/drain diffusion region
107
a
is shown in FIG.
1
B and can be operated by two methods. The first operation method is that the stored electrons in the floating-gate
102
are tunneled through the thin gate-oxide layer
101
into the semiconductor substrate
100
using Fowler-Nordheim tunneling for the erasing operation; the channel hot-electron injection is used for the programming operation. For this kind of programming and erasing, the junction depth of the source/drain diffusion region can be made to be shallower and the doping concentration in the source/drain diffusion region can be higher. Although the punch-through effect of the device can be alliviated but is still a bottleneck of scaling. The second operation method is that the electrons in the source diffusion region
107
a
are tunneled through the thin gate-oxide layer
101
into the floating-gate
102
using Fowler-Nordheim tunneling for the erasing operation and the stored electrons in the floating-gate
102
are tunneled through the thin gate-oxide layer
101
into the drain diffusion region
107
a
for the programming operation. For this kind of programming and erasing, the junction depth of the source/drain diffusion region must be deeper and the doping concentration in the source/drain diffusion region can be lighter. However, the junction depth of the source/drain diffusion region must be shallower as the stack-gate length is scaled down, resulting in longer programming and erasing time.
As the stack-gate flash memory devices are integrated to form a memory array, the major issues encountered are device isolation, device contact, and interconnection. Basically, device isolation can be divided into two categories: local oxidation of silicon (LOCOS) and shallow-trench-isolation (STI). In general, the shallow-trench-isolation method occupies less silicon surface area and is more suitable for high-density memory fabrication. The device contact and the device interconnection in a memory array are arranged through a specified memory architecture and are formed in a matrix in order to have a higher packing density. The architecture of a flash memory array can be NOR, NAND, AND, and DINOR etc., in which NOR and NAND are frequently used. However, for any architecture, a plurality of isolation-region lines are formed over a semiconductor substrate in parallel having a plurality of active-region lines formed therebetween, a plurality of flash memory cells are formed regularly on each of active-region lines having the control-gate layer of each flash memory cell run over the field-oxides in the isolation-region lines to form a plurality of word lines perpendicular to the plurality of isolation-region lines, and the flash memory cells in each of active-region lines form a column and are interconnected by the common source/drain diffusion regions. For a NOR-type architecture, the common-drain diffusion regions of flash memory cells in each column have the contacts formed and are connected to a bit line perpendicular to the plurality of word lines, and a plurality of bit lines are then formed; the common-source diffusion regions of flash memory cells in each row are interconnected by possible means to form a common-source bus line in parallel with the word line, and a plurality of common-source bus lines are formed.
The common-source bus line of the prior arts is formed by first removing the field-oxides in the isolation-region lines and is then implanted with a high dose of doping impurities into the active regions and the isolation regions along a common-source bus line to form a buried common-source line, as shown in FIG.
1
C and
FIG. 1D
, where
FIG. 1C
shows a cross-sectional view of a buried common-source line for LOCOS isolation;
FIG. 1D
shows a cross-sectional view of a buried common-source line for STI isolation. It is clearly seen from FIG.
1
C and
FIG. 1D
that the bird's beak regions
107
c
of LOCOS isolation are difficult to be implanted uniformly, resulting in higher buried resistance; however, the steep sidewalls
107
c
of STI isolation are much difficult to be implanted uniformly. It should be noted that deeper buried layer doped or implanted isn't favorable to the shallower source/drain diffusion region needed for the scaled stack-gate flash memory device. Moreover, the parasitic junction capacitance and the leakage current between the buried common-source line and the semiconductor substrate can't be overlooked.
The bit line of the prior arts which is formed by the first interconnect-metal layer is connected to a silicide layer formed on a common-drain diffusion region through a contact hole filled with a tungsten plug over a barrier-metal layer, the contact size is in general larger than the minimum-feature-size in order to have a proper contact area over the common-drain diffusion region and becomes a technical bottleneck to be solved for high-density flash memory array. Moreover, the junction depth of the common-drain diffusion regions becomes shallower as the stack-gate flash memory device is scaled down, the contact problem between the bit line and the shallow common-drain diffusion region can't be overlooked. As the junction depth of the common source/drain diffusion regions becomes shallower, the higher series resistance resulting from the interconnection of stack-gate flash memory cells becomes an obstacle for high-speed read operation, together with the high series resistance of the buried common-source line formed at the source terminals of the source select transistors, the advantages of NAND-type architecture become disappeared.
In addition, the word line is connected with each of stack-gate flash memory cells in a row through the control-gate layer, the control-gate layer of the prior arts is made of a tungsten-silicide layer formed over a doped polycrystalline-silicon layer or a si
Le Dung A
Pro-Techtor International
Silicon Based Technology Corp.
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