Methods of fabricating a single transistor floating body...

Details Methods of fabricating a single transistor floating body... Methods of fabricating a single transistor floating body...

2006-01-19

2008-03-04

Quach, T. N. (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S272000, C257SE21428

Reexamination Certificate

active

07338862

ABSTRACT:
Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region within the body layer. A recess region is formed in the floating body region. A gate electrode is formed in the recess region. Impurity ions of a first conductivity type are implanted into a portion of the floating body region on a first side of the recess region to define a source region and into a portion of the floating body on an opposite side of the recess region to define a drain region to provide a floating body.

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Office Action for Korean Patent Application No. 10-2005-0027239 mailed on May 16, 2006.
Figure 7.20: Cross section of a 0.6 μm SOI BiCMOS technology and Figure 7.21: Cross Section of a Vertical SOI Bipolar Transistor (source unknown) (1998).
English Translation of Office Action for Korean Patent Application No. 10-2005-0027239 mailed on May 16, 2006.

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