Methods of fabricating a MOSFET

Details Methods of fabricating a MOSFET Methods of fabricating a MOSFET

2003-07-25

2004-09-21

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06794233

ABSTRACT:

TECHNICAL FIELD
The present disclosure pertains to methods of fabricating a semiconductor device and, more particularly, to methods of fabricating a metal-oxide-semiconductor field effect transistor (hereinafter referred to as “MOSFET”) that is able to ensure an effective channel length.
BACKGROUND
Line width in semiconductor devices has been continuously reduced due to high integration of semiconductor devices. As the line width in a gate electrode shrinks, the length of the channel decreases. In addition, the threshold voltage starts to decrease appreciably with the channel length. This phenomenon is typically called the “short channel effect.” Accordingly, various technologies to reduce such short channel effect have been proposed.
Preferably, the short channel effect is obviated for high integration of a semiconductor device. An example of a method for obviating the short channel effect is to form lightly doped drain (LDD) regions.
FIGS. 1
a
through
1
d
are cross-sectional views illustrating a process of fabricating a MOSFET with LDD regions. Referring to
FIG. 1
a
, a gate oxide layer
2
a
and a polysilicon layer
2
b
as a conducting layer for a gate, are formed on a semiconductor substrate
1
. The polysilicon layer
2
b
and gate oxide layer
2
a
are etched to form a polysilicon gate electrode
3
. Then, as shown in
FIG. 1
b
, a low-concentration ion implantation and a thermal treatment process are used to form LDD regions
6
on the surface of the substrate at both sides of the polysilicon gate electrode
3
.
Next, referring to
FIG. 1
c
, the whole area of the semiconductor substrate
1
including the polysilicon gate electrode
3
is covered with an insulating layer, and the insulating layer is blanket-etched to form a gate spacer
5
on both lateral walls of the polysilicon gate electrode
3
. Then, as shown in
FIG. 1
d
, a dopant is implanted into the substrate part at both sides of the polysilicon gate electrode
3
including the spacer
5
by means of high-concentration ion implantation. After the ion implantation, a thermal treatment process is conducted to form source and drain regions
8
having LDD regions
6
.
However, in the above-described method of fabricating a MOSFET, it is difficult to ensure an effective channel length because the LDD regions and source and drain regions are formed by ion implantation and thermal treatment.


REFERENCES:
patent: 5372957 (1994-12-01), Liang et al.
patent: 5672525 (1997-09-01), Pan
patent: 5726477 (1998-03-01), Williams et al.
patent: 5792699 (1998-08-01), Tsui
patent: 5920774 (1999-07-01), Wu
patent: 6008099 (1999-12-01), Sultan et al.
patent: 6091118 (2000-07-01), Duane
patent: 6153520 (2000-11-01), Chen
patent: 6214656 (2001-04-01), Liaw
patent: 6221746 (2001-04-01), Huang et al.
patent: 6242334 (2001-06-01), Huang et al.
patent: 6323094 (2001-11-01), Wu
patent: 1019990066930 (1999-12-01), None
patent: 1020000019690 (2000-04-01), None
patent: 1020000048326 (2000-08-01), None

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