Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-14
2004-06-08
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S201000, C438S211000, C438S262000, C257S314000
Reexamination Certificate
active
06746918
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating a scaled non-volatile semiconductor memory device and, more particularly, to methods of fabricating a stack-gate non-volatile semiconductor memory device having a tapered floating-gate structure and its contactless memory arrays for high-density mass storage applications.
2. Description of Related Art
A non-volatile semiconductor memory device is known to store charges in an isolated gate being known as a floating gate by means of either Fowler-Nordheim tunneling or hot-electron injection through a thin tunneling-dielectric layer from a semiconductor substrate for programming and to remove or erase charges stored in the isolated gate by means of Fowler-Nordheim tunneling through a thin tunneling-dielectric layer to the source diffusion region of a semiconductor substrate or a control gate. Basically, the cell size of a non-volatile semiconductor memory device must be scaled down for high-density mass storage applications and the cell structure must be developed toward low-voltage, low-current and high-speed operation with high endurance and high retention.
In general, the non-volatile semiconductor memory devices of the prior arts can be divided into two categories, based on the cell structure: a stack-gate structure and a split-gate structure. The stack-gate structure is known to be a one-transistor cell, in which the gate length of a cell can be defined by using a minimum-feature-size (F) of technology used. However, the split-gate structure including a floating gate and a select gate is known to be a 1.5-transistor cell. Therefore, the stack-gate structure is more suitable for high-density mass storage applications than the split-gate structure.
FIG. 1A
shows a cross-sectional view of a stack-gate non-volatile semiconductor memory device in the channel-length direction, in which a thin tunneling-oxide layer
101
is formed over a semiconductor substrate
100
; a doped polycrystalline-silicon layer
102
being acted as a floating gate is formed over the thin tunneling-oxide layer
101
; an intergate-dielectric layer
103
of preferably an oxide-nitride-oxide (ONO) structure is formed on the floating gate
102
; a doped polycrystalline-silicon layer
104
capped with a silicide layer either using polycide or salicide technology is formed over the intergate-dielectric layer
103
to act as a control gate; a source diffusion region is formed with a double-diffused structure having a shallow heavily-doped diffusion region
106
a
formed within a deeper moderately-doped diffusion region
105
a
; a drain diffusion region
106
b
is formed by a shallow heavily-doped diffusion region in the semiconductor substrate
100
; and a pair of sidewall dielectric spacers
106
are formed over sidewalls of a gate stack.
Basically, the operation principle of a stack-gate non-volatile semiconductor memory device shown in
FIG. 1A
had been described by Mukherjee et al. in U.S. Pat. No. 4,698,787. The programming of a stack-gate non-volatile semiconductor memory device shown in
FIG. 1A
can be accomplished by applying a relatively high positive-voltage to a control gate
104
, a moderately high positive-voltage to a drain
106
b
, and a source
106
a
is grounded. A high lateral electric field near the drain edge is used to generate hot-electrons and the generated hot-electrons with an energy higher than the interface barrier between the conduction bands of a thin tunneling-oxide layer
101
and the semiconductor substrate
100
are injected into a floating gate
102
and stored there. The erasing of the stack-gate non-volatile semiconductor memory device shown in
FIG. 1A
can be accomplished by applying a relatively high negative-voltage to the control gate
104
and a moderately high positive-voltage to the source
106
a
, and the drain
106
b
is usually kept floating. The stored electrons in the floating gate
102
are then tunneling from the floating gate
102
to the double-diffused source structure
106
a
,
105
a
by a high electric field across the thin tunneling-oxide layer
101
over the double-diffused source structure. The double-diffused source structure is mainly used to eliminate the band-to-band tunneling effects during erasing and a deeper double-diffused source junction is therefore needed to have a large overlapping area for a thin tunneling-oxide layer in order to increase the erasing speed.
Apparently, as the gate length of a stack-gate non-volatile semiconductor memory device shown in
FIG. 1A
is scaled for high-density mass storage applications, there is an important issue encountered: the deeper double-diffused source structure becomes an obstacle for a scaled stack-gate length because the punch-through effect becomes serious for programming using hot-election injection as stated above. It is, therefore, an objective of the present invention to provide a non-volatile semiconductor memory device having a tapered floating-gate structure and its fabrication method for a scaled stack-gate length to alleviate the problems encountered by the prior arts.
As the stack-gate non-volatile semiconductor memory device shown in
FIG. 1A
is implemented as a cell of a memory array, for example: a NOR-type memory array, the source of the stack-gate non-volatile semiconductor memory devices in a column are connected each other by a common-source line (SL) and the nearby two columns use the same common-source line (SL). The common-source line (SL) for nearby two columns is in general implemented by first completely removing the field-oxides in the field-oxide isolation regions using a non-critical masking step and then implanting doping impurities into a semiconductor substrate to form a buried common-source line.
FIG. 1B
shows a cross-sectional view along a buried common-source line for LOCOS isolation. It is clearly shown that a non-uniform doping depth
106
c
,
106
d
would occur over the side-slope formed by LOCOS, resulting in higher buried common-source line resistance. This phenomenon would be more serious for shallow-trench-isolation (STI) when compared to LOCOS isolation, as shown in FIG.
1
C.
There are several methods proposed to improve the buried common-source line resistance. U.S. Pat. No. 6,211,020 B1 had proposed a plasma implantation technique to improve the non-uniform doping depth resulting from conventional ion-implantation. However, the buried common-source line resistance is still high because the junction depth of a plasma implantation will be limited by the source junction depth of a scaled non-volatile semiconductor memory device. Moreover, a large junction capacitance of the buried common-source line together with a high parasitic resistance of the buried common-source line may reduce the operation speed of a non-volatile semiconductor memory array for high-density mass storage applications. U.S. Pat. No. 6,221,718 B1 had proposed the parallel common bit-lines for the source/drain diffusion regions of all cells using a doped polycrystalline-silicon layer. The doped polycrystalline-silicon layer must be thinner than the thickness of the floating gate in order to run an intergate ONO layer and a control gate. It is clearly seen from the formed structure that a very high parasitic capacitance between the control gate and the common bit-lines is expected. U.S. Pat. No. 6,211,012 B1 had described a conductive layer including tungsten, aluminum or doped polycrystalline-silicon as the common-source lines and the landing pads for the bit-line contacts. A planarized CVD-oxide layer and a critical alignment mask step are required to pattern the landing pads. Moreover, a critical mask is also required to register the stack-gate over the pre-isolated substrate shown. It is, therefore, another objective of the present invention to provide a contactless structure with the common-source/drain conductive bus lines having very low common bus-line resistance and capacitance, and the highly conductive landing islands for the scaled stack-gate non-volatile
Le Thao X.
Pham Long
Pro Techtor International Services
Silicon Based Technology Corp.
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