Methods for tracing faults in memory components

Details Methods for tracing faults in memory components Methods for tracing faults in memory components

2001-02-09

2004-03-02

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06701472

ABSTRACT:

TECHNICAL FIELD
The present invention is relates to the field of memory devices, and in particular, to methods for tracing faults in memory components.
BACKGROUND
Memory components, for example, FIFO (first in first out) and SDRAM components, prior to their release are typically tested, so as not to be released with faults. Contemporary testing methods for tracing problems in memory components on a circuit, typically a chip on a board, are usually conducted with procedures that test based on the overall current in a line, or the overall current in each individual bit.
Typical testing procedures where overall current in a line is analyzed involve processes where an all “zeros” word is written and read and followed by an “ones” word that is written and read, with this alternating pattern continuing as necessary. If expressed in Hexadecimal (base 16 also known as hex), a typical testing pattern is as follows:
0x00000000
0xFFFFFFFF
0x00000000
0xFFFFFFFF
.
.
.
0x00000000
0xFFFFFFFF
This method exhibits drawbacks, as after a few lines, the memory component under test does not respond to current changes. This may be due to a situation, where a bit of one value is surrounded by bits of other values, with the difference between these values great, whereby the greater value bits effect the lesser value bit to behave similarly with respect to current changes. Accordingly, the memory component simply stops responding to the current changes. This method fails to cause a memory fault, as it fails to stress or fatigue the memory component. Therefore, it will not be known if any actual bits are defective, for the memory component failed to respond to the current change.
Alternately, methods have been developed to look at the overall current in each individual bit. Some exemplary methods that look at the overall current in these bits are commonly known as the “Chessboard”, “running one” or “running zero” methods. These methods typically involve sequences as follows (in binary):
0000000000000000
1000000000000000
0100000000000000
0010000000000000
.
.
.
0000000000000001
This method also exhibits drawbacks, in that since the current remains the same from the second line to the end of the sequence, extreme current changes will not be produced in the memory component. As a result, there is a likelihood that defective bits will be missed and thus, not detected.
In a testing method known as random, single words are written and read into memory components. These words need only differ by one bit. There are not any rules or order to the words, as the objective is merely to write and read as many possible word combinations into the memory component as possible. This process exhibits drawbacks as it fails to fatigue the memory components, as current may or may not have changed and can not detect specific defective bits.
One other conventional approach is a ramp method, performed by increasing by “1” as follows:
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
*
*
*
11111111
This ramp method exhibits drawbacks in that only defective words and not specific defective bits can be determined. This is again because this testing sequence simply does not fatigue the memory component sufficiently, as the current is not changed drastically upon incrementing by “1”.
SUMMARY
The present invention improves on conventional simulators, by providing a testing method that can detect and allow for tracing of faults in memory components by looking at overall current in the bits, as well as looking at the influence of current in all of the individual bits with respect to other similar bits in the memory component being tested. Embodiments are directed to methods for tracing faults in memory components and in particular, to methods having words, formed of bits, that are composed of all “zeros” or all “ones” except for one bit of the respective word, designated as a “unique” bit, that is moved or shifted in each subsequent word.
Each word, with the unique bit that has been shifted, also known as the shifted bit, and its complement word (or complement), defining a cycle (also known as a compliment pair), are grouped with other cycles in blocks to define a testing sequence or pattern, and written into a memory component. By writing each word with its complement word, followed by words having the shifted bit, and their respective complements, extreme current changes, from each of the complement pairs, occur contemporaneous with changed conditions for individual bits, from the shifting. The shifting in the presence of these extreme current changes creates different bit combinations, where one bit is different from all of the other bits of the combination and each combination itself is different by one bit. The current change coupled with these changed bit combinations stresses or fatigues the memory component, and allows for the evaluation of single bits.
The written words are then read from the memory component being evaluated, and compared with the written words to detect differences. If a difference in corresponding words is detected, an error message is generated and sent, indicative of a fault in the memory component under test.
As a result of these methods, defective individual bits can be specifically identified. This method is easily implemented on conventional computers and other testing equipment. It is economical, as it does not require any special instruments or accessories. Additionally, this method is quick and reliable for determining faults in memory components.
Embodiments of the present invention are directed to methods, systems and computer-usable storage media for testing memory components, that include providing a testing sequence comprising at least a first cycle and at least one subsequent cycle, typically N subsequent cycles. Each cycle includes a first word of N bits and a second word of N bits, with the second word defined as the complement of said first word. Subsequent cycles, after the initial first cycle, typically include a first word having at least one bit shifted with respect to the corresponding bit in the first word of the previous cycle, with the shifted bit being shifted in the direction from least significant bit to most significant bit. The testing sequence is then written into a memory component or components and then read from the memory component or components. The written words then read and compared with the written words, typically for a correspondence therebetween, to allow for analysis of bits, including detection of defective bits, and thus, faults, in the tested memory component or component. This may be through an error message or the like and sent to the computer or the like of the testing party.


REFERENCES:
patent: 4061908 (1977-12-01), DE Jonge et al.
patent: 4559626 (1985-12-01), Brown
patent: 4782487 (1988-11-01), Smelser
patent: 4958345 (1990-09-01), Fujisaki
patent: 5375091 (1994-12-01), Berry, Jr. et al.
patent: 5633877 (1997-05-01), Shephard et al.
patent: 5881221 (1999-03-01), Hoang et al.
patent: 40 01 563 (1991-07-01), None
patent: 0 291 283 (1988-11-01), None

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