Methods for testing a group of semiconductor devices...

Details Methods for testing a group of semiconductor devices... Methods for testing a group of semiconductor devices...

2000-06-30

2002-11-19

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S226000

Reexamination Certificate

active

06483759

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 1999-26594, filed on Jul. 2, 1999, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a test power supply circuit of a semiconductor device.
BACKGROUND OF THE INVENTION
As integration levels of semiconductor chip devices increase, the test time for evaluating the characteristics of a fabricated semiconductor chips also increases. This increases disproportionately the cost of the semiconductor chip. To solve this problem, it is required to simplify the test algorithms and improve testing circumstances.
A recent main method for preventing increase in the test time is a multi-test method. A number of semiconductor chips formed on a wafer are tested at the same time.
Referring to
FIG. 1
, a conventional wafer has a plurality of semiconductor chips
3
formed on a silicon substrate
1
. Direct current (hereafter referred to as “DC”) and alternating current (hereafter referred to as “AC”) characteristics of each of the semiconductor chips
3
are tested in the test step. Since all are tested simultaneously, this reduces test time.
Scribe lines
5
delineate the boundaries regions between the semiconductor chips
3
. After testing, the semiconductor chips
3
are cut from the wafer
1
along the scribe lines
5
, and packed.
Based on “Ohm's Law”, electric characteristics such as open or short of each of the semiconductor chips
3
(i.e., short or not of power supply voltage V
CC
and ground voltage V
SS
) are tested at the DC characteristic test operation. Conditions such as power supply voltage margin, timing, and temperature are applied to each of the semiconductor chips
3
, thereby testing circuit operation of each of the semiconductor chip
3
and a storage status.
A test system for testing the semiconductor chips
3
tests the DC and AC characteristics of each of the chips
3
through a probe card by loading and then aligning the wafer of these chips. The probe card includes a very fine needle that is fixed on a printed circuit board (PCB). A signal generated from the test system is transferred to each circuit of the semiconductor chips
3
through the needle of the probe card, and a signal generated from a circuit in the semiconductor chip
3
is transferred to the test system through the probe card.
In general, a plurality of (e.g., four) semiconductor chips are simultaneously tested.
Referring to
FIG. 2
, a physical arrangement is shown for testing 4 devices DUT
1
10
, DUT
2
20
, DUT
3
30
, DUT
4
40
, which are arranged at the corners of a rectangle. Test-targeted circuits
10
,
20
,
30
, and
40
are tested by connecting power pads V
CC
and V
SS
, and input/output pads I
00
, I
01
, . . . I
015
with a mutual-sharing arrangement.
During the test operation, a test system supplies power supply voltage V
CC
, ground voltage V
SS
, and input signals I
00
, I
01
. . . I
015
to the circuits of the chips, through each needle of a probe card and each pad (not shown) of the chips. And, the test system receives the voltages V
CC
and V
SS
, and output signals O
1
, O
2
, . . . , O
14
, and O
15
(not shown) through the pad and the needle of the probe card.
The sharing arrangement of the power pads V
CC
and V
SS
has to a poignant problem at AC test operation. This is illustrated by assuming that device
20
has a defect, illustrated by resistor R
2
as partially shorting VCC and VSS of DUT
2
20
. The resistor R
2
generates a large amount of leakage current. In this case, the power supply voltage V
CC
supplied to DUT
20
, and also to the other circuits
10
,
30
, and
40
goes down to a low level, due to the sharing arrangement.
While this is expected during testing for DC-type defects, it is a big problem while testing for AC-type defects. This causes increase in test time of a semiconductor fabrication device, and considerably reduces a yield of a fabrication process.
SUMMARY OF THE INVENTION
The invention overcomes the problems of the prior art.
The invention provides methods for testing a plurality of semiconductor devices. The devices are connected in a group, and checked for DC-type defects. Those identified to have such a defect are electrically disconnected from the group. Disconnection is by electrical action, while maintaining the physical connection. Thus the defective are also effectively disconnected from further group testing. Then testing in the AC mode is performed. The disconnected devices do not sense the AC testing, and the DC-type defect does not affect the AC testing of the remaining devices.
The method of the invention can be practiced with a number of arrangements. For example, the testing apparatus can have individualized leads that disconnect for individual devices, while permitting the remaining devices to be tested for AC-type defects.
The invention also provides semiconductor devices, which are specially made to be amenable to testing according to the method of the invention. These include additional pads, and a special circuit that include at least one fuse. Disconnection is by cutting the fuse of a device identified to be defective. The subsequent AC testing is by applying the power supply and a ground through the additional pads. The fuse will determine which power is applied to the power line of the device.
A further understanding of the nature and advantage of the invention herein may be realized by reference to the remaining portions of the specification and the attached drawings.


REFERENCES:
patent: 4835458 (1989-05-01), Kim
patent: 5381373 (1995-01-01), Ohsawa
patent: 5808947 (1998-09-01), McClure
patent: 6031755 (2000-02-01), Ozawa

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