Methods for selective placement of dislocation arrays

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S938000, C438S301000

Reexamination Certificate

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07494881

ABSTRACT:
Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.

REFERENCES:
patent: 4885614 (1989-12-01), Furukawa et al.
patent: 5032893 (1991-07-01), Fitzgerald, Jr. et al.
patent: 5084411 (1992-01-01), Laderman et al.
patent: 5091767 (1992-02-01), Bean et al.
patent: 5156995 (1992-10-01), Fitzgerald, Jr. et al.
patent: 5256550 (1993-10-01), Laderman et al.
patent: 5323031 (1994-06-01), Shoji et al.
patent: 5357119 (1994-10-01), Wang et al.
patent: 5659187 (1997-08-01), Legoues et al.
patent: 5668387 (1997-09-01), Streit et al.
patent: 5801085 (1998-09-01), Kim et al.
patent: 5810924 (1998-09-01), Legoues et al.
patent: 5828114 (1998-10-01), Kim et al.
patent: 5844260 (1998-12-01), Ohori
patent: 5937274 (1999-08-01), Kondow et al.
patent: 6037615 (2000-03-01), Matsuyama et al.
patent: 6555880 (2003-04-01), Cabral, Jr. et al.
patent: 6576532 (2003-06-01), Jones et al.
patent: 7049627 (2006-05-01), Vineis et al.
patent: 2002/0185686 (2002-12-01), Christiansen et al.
patent: 2003/0089901 (2003-05-01), Fitzgerald
patent: 2003/0227057 (2003-12-01), Lochtefeld et al.
patent: 2004/0005740 (2004-01-01), Lochtefeld et al.
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 0402209 (1990-12-01), None
patent: 0523487 (1993-01-01), None
patent: 1197992 (2002-04-01), None
Nabarro, Theory of Crystal Dislocations (1967) pp. 33.
Houghton, “Strain relaxation kinetics in Si1—xGexheterostructures,”J. Appl. Phys., vol. 70, No. 4 (Aug. 15, 1991) pp. 2136-2151.
Bruel et al., “® Smart Cut”: A Promising New SOI Material Technology,178 Proceedings 1995 IEE International SOI Conference(Oct. 1995) pp. 178-179.
Akatsu et al., Wafer bonding of different III-V compound semiconductors by atomicv hydrogen surface cleaning,:Journal of Applied Physics, vol. 90, No. 8 (Oct. 15, 2001), pp. 3856-3862.
Belgal et al., “A New Mechanism of Pipeline Defect Formation in CMOS Devices,”International Reliability Physics Symposium, (1994), pp. 399-404.
Bulsara et al., “Relaxed InxGa1-xAs graded buffers grown with organometallic vapor phase epitaxy on GaAs,”Applied Physics Letters, vol. 72, No. 13 (Mar. 30, 1998), pp. 1608-1610.
Culliset al., “Growth ripples upon strained SiGe epitaxial layers on Si and misfit dislocation interactions,” Journal of Vacuum Science and Technology, A 12(4) (Jul./Aug. 1994), pp. 1924-1931.
Currie et al., “CVarrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates,”Journal of Vacuum Science and Technology, B 19(6) (Nov./Dec. 2001), pp. 2268-2279.
De Boeck et al., “Growth and structural characterization of embedded InAsSb on GaAs-coated patterned silicon by molecular beam epitaxy,”Applied Physics Letters, 58 (9) (Mar. 4, 1991), pp. 928-930.
Feenstra et al., “Scattering from strain variations in high-mobility Si/SiGe heterostructures,”Journal of Applied Physics, 78 (10) (Nov. 15, 1995), pp. 6091-6097.
Fitzgerald et al., “Dislocation dynamics in relaxed graded composition semiconductors,”Materials Science and Engineering, B67 (1999), pp. 53-61.
Godbey et al., “A Si0.7Ge0.3 strained-layer etch stop for the generation of thin layer undoped silicon,”Applied Physics Letters, 56 (4) (Jan. 22, 1990), pp. 373-375.
Gonzales et al., “Advantages of thin interfaces in step-graded buffer structures,”Materials Science and Engineering, B44 (1997), pp. 41-45.
Gray et al., “Effect of Anisotropic Strain on the Crosshatch Electrical Activity in Relaxed GeSi Films,”Physical Review Letters, vol. 86, No. 16 (Apr. 16, 2001), pp. 3598-3601.
Ha et al., “Anomalous Jundtion Leakage Current Induced by STI Dislocations and Its Impact on Dynamic Random Access Memory Devices,”IEEE Transactions on Electron Devices, vol. 46, No. 5 (May 1999), pp. 940-946.
Knall et al., “The use of graded InGaAs layers and patterned substrates to remove threading dislocations from GaAs on Si,”Journal of Applied Physics, 76 (5) (Sep. 1, 1994), pp. 2697-2702.
MacElwee et al., “High-Performance Fully Depleted Silicon-on-Insulator Transistors,”IEEE Transactions on Electron Devices, vol. 37, No. 6 (Jun. 1990), pp. 1444-1451.
McCarthy et al., “Effect of threading dislocations on AlGaN/heterojunction bipolar transistors,”Applied Physics Letters, vol. 78, No. 15 (Apr. 9, 2001), pp. 2235-2237.
Meshkinpour et al., “Role of misfit dislocations on pseudomorphic high electron mobility transistor,”Applied Physics Letters, 66 (6) (Feb. 6, 1995), pp. 748-750.
Mica et al., “Crystal defects and junction properties in the evolution of device fabrication technology,”Journal of Physics: Condensed Matter, 14 (2002), pp. 13403-13410.
Momose et al., “Dislocation-free and lattice-matched Si/GaP1-xNx/Si structure for photo-electronic integrated systems,”Applied Physics Letters, vol. 79, No. 25 (Dec. 17, 2001), pp. 4151-4153.
Mooney et al., “Scanning x-ray microtopographs of misfit dislocations at SiGe/Si interfaces,”Applied Physics Letters, vol. 79, No. 15 (Oct. 8, 2001), pp. 2363-2365.
Mooney et al., “SiGe Technology: Heteroepitaxy and High-Speed Microelectronics,”Annual Review of Materials Science, 30 (2000), pp. 335-362.
Mooney et al., “Thermal Stability of Strained Si on Relaxed Si1-xGex Buffer Layers,”Materials Research Society Symposium Proceedings, vol. 686 (2002), pp. A1.2.1-A1.2.6.
Morris et al., “Structure property anisotropy in lattice-mismatched single heterostructures,”Journal of Applied Physics, 71 (5) (Mar. 1, 1992), pp. 2321-2327.
Ohashi et al., “Simulation of dislocation accumulation in ULSI cells with STI structure,”Applied Surface Science, (2003), pp. 1-7.
Rammohan et al., “Study of μm-scale spatial variations in strain of a compositionally step-graded InxGa1-x/GaAs(001) heterostructure,”Applied Physics Letters, 66 (7) (Feb. 13, 1995), pp. 869-871.
Samavedam et al., “Novel dislocation structure and furface morphology effects in relaxed Ge/Si-Ge(graded)/Si structures,”Journal of Applied Physics, 81 (7) (Apr. 1, 1997), pp. 3108-3116.
Sleight et al., “Stress induced Defects and Transistor Leakage for Shallow Trench Isolated SOI,”IEEE Transactions on Electron Devices, vol. 20, No. 5 (May 1999), pp. 248-250.
Soh et al., “Relation Between Etch Pit Pairs And Pipeline Defects In CMOS Device,”International Reliability Physics Symposium, pp. 244-248.
Su et al., “Effects of Dislocation and Bulk Micro Devects on Device Leakage,” Semicon Taiwan 2001, pp. 1-4.
Thompson et al., “NMOS Device Characteristics in Electron-Beam-Recrystallied SOI,”IEEE Transactions on Electron Devices, vol. 40, No. 7 (Jul. 1993), pp. 1270-1276.
Tromp et al., “Advanced in Situ Ultra-High Vacuum Electron Microscopy: Growth of SiGe on Si,”Annual Review of Materials Science, 30 (2000), pp. 431-449.
Wang et al., “Pipeline Defects in CMOS MOSFET Devices Caused by Swami Isolation,”International Reliability Physics Symposium, (1992), pp. 85-90.
Williams et al., Evaluation of the Yield Impact of Epitaxial Devects on Advanced Semicondfuctor Technologies, 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 1-7.
Wu, “Novel Etch-Stop Materials for Silicon Micromachining,” Master of Science Thesis, Massachusetts Institute of Technology, 1997.
Yamada et al., “Static analysis of off-axis crystal film growth onto a lattice-mismatched substrate,”Applied Physics Letters, vol. 79, No. 5 (Jul. 30, 2001), pp. 608-610.
International Search Report for International Application No. PCT/US03/23804, Mar

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