Methods for reducing wordline sheet resistance

Details Methods for reducing wordline sheet resistance Methods for reducing wordline sheet resistance

2008-01-01

2008-01-01

Kebede, Brook (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21680, C257SE21694

Reexamination Certificate

active

11015154

ABSTRACT:
The present invention is directed to forming memory wordlines having a relatively lower sheet resistance. In one embodiment, a control-gate poly layer including a first and a second poly-Si portion is deposited. a The first poly-Si portion is deposited on a semiconductor substrate using a first precursor gas flow rate. A The second poly-Si portion is deposited on the first poly-Si portion using a second precursor gas flow rate, where the second precursor flow rate higher than the first precursor gas flow rate. A tungsten silicide layer is then deposited. A wordline is formed from a stacked film of the control-gate poly layer and tungsten silicide layer. The control-gate poly layer and tungsten silicide layer are then patterned to form a gate electrode, and a implantation process is made, after or before, forming the tungsten silicide layer.

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