Methods for reducing profile variation in photoresist trimming

Details Methods for reducing profile variation in photoresist trimming Methods for reducing profile variation in photoresist trimming

2001-09-06

2003-11-25

Huff, Mark F. (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Removal of imaged layers

C430S313000, C430S314000, C430S324000, C216S037000, C216S046000, C216S063000, C438S694000, C438S695000

Reexamination Certificate

active

06653058

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the process of trimming photoresist material on semiconductor wafers and, more particularly, to trimming a photoresist material while reducing the variation of the critical dimension between photoresist lines and maximizing photoresist budget.
FIG. 1
is a cross-sectional view illustrating several conventional layers of a semiconductor wafer
10
. Semiconductor wafer
10
includes a semiconductor substrate
12
formed of, e.g., silicon, that supports intermediate layers
15
. Intermediate layers
15
may, for example, include a first layer
14
formed of either a conductive material (e.g. polysilicon) or a dielectric material (e.g. SiO
2
) depending on the type of device that is being fabricated. Intermediate layers
15
also may include a second layer
16
, such as a hard mask layer or an anti-reflective coating (ARC) layer. For ease of illustration, intermediate layers
15
is shown comprising only two layers, but as is well known in the art, more layers may be provided.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. Conventionally, a layer of photoresist material
18
is deposited onto semiconductor wafer
10
over intermediate layers
15
, and then patterned by a suitable process such as photolithography. In general, the wafer is exposed to light filtered by a reticle, which is a glass plate that is patterned with the desired integrated circuit layer features.
After passing through the reticle, the light impinges upon the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can be used to remove either the exposed regions (in the case of positive photoresist materials) or the unexposed regions (in the case of negative photoresist materials) of the photoresist material. In the case of positive photoresist materials, the light changes the structure and chemical properties of the photoresist material creating a number of polymerized photoresist sections. These polymerized photoresist sections are then removed using a solvent in a development process leaving a number of photoresist lines. Thereafter, the wafer is etched to remove the material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the wafer.
FIG. 2A
is a more detailed view of photoresist layer
18
after it has been patterned into a photoresist mask. In the process described above, the photoresist sections that were polymerized are removed, leaving photoresist lines
18
a-d,
which protect underlying layers from etching.
One important characteristic of photoresist lines is known as an aspect ratio, which compares the vertical space between lines with the horizontal space. For example, the space between photoresist lines
18
a
and
18
b
would have an aspect ratio of approximately 1:2, while the space between photoresist lines
18
b
and
18
c
would have an aspect ratio of about 5:2.
Each photoresist line
18
a-d
has a line width or critical dimension CD
1
, which determines the width of lines that will be etched in intermediate layers
15
. Each photoresist line
18
a-d
also has a height, which is also known as a resist budget RB
1
. During the process of etching intermediate layers
15
, photoresist lines
18
a-d
are also etched. Therefore, resist budget RB
1
represents the amount of resist that may be consumed by the etching process. For ease of illustration, only four photoresist lines
18
a-d
are shown, however, as is well known in the art, numerous photoresist lines
18
a-d
may be formed to produce the desired feature geometries. The feature geometries will in turn enable production of the electrical interconnections intended by the manufacturer, and enable the production of a functioning integrated circuit.
One technique that engineers use to increase the operating speeds of semiconductor devices is by reducing the sizes of conductive lines within the device. Although much improvement has occurred in photolithography systems to enable the fabrication of small features sizes, current lithographic tools are still unable to define feature sizes much below about 0.18 microns. Unfortunately, the costs of developing a photolithography system to define feature sizes below 0.18 microns would be involve the manufacturing of a new tool, and therefore be prohibitively expensive. Therefore, plasma etching has been considered as a method of further reducing the critical dimension CD
1
, which defines feature sizes, of photoresist lines
18
a-d
. This technique is called photoresist trimming.
FIG. 2B
illustrates patterned photoresist layer
18
during the process of photoresist trimming. After photolithography has been performed, producing photoresist lines
18
a-d
of, for example, about 0.18 microns, a plasma etch is performed to further reduce the critical dimensions. Photoresist lines
18
a-d
are bombarded with an etchant flow
20
/
20
′, such as oxygen ions, using a low RF bias power to create a plasma. Etchant flow
20
′ is distinguished from etchant flow
20
to show ions traveling toward the photoresist lines
18
a-d
at somewhat variable angles.
As shown in
FIG. 2B
, the degree of exposure that each photoresist line
18
a-d
has with the ion bombardment varies depending on its proximity to that of other photoresist lines. If a photoresist line is located in an open area, the sidewalls of the photoresist line are in general, fully exposed to angled etchant flow
20
′. However, if a photoresist line is located in a dense area, the amount of etchant flow
20
′ that reaches the lower portions of photoresist sidewalls may be greatly reduced because a large amount of etchant flow
20
′ is blocked by the neighboring photoresist line.
For example, photoresist line
18
a
is isolated from other photoresist lines
18
b-d
. Therefore, photoresist lines
18
b-d
do not affect the exposure of photoresist line
18
a
to etchant flow
20
′. However, because photoresist line
18
c
is located in close proximity to photoresist lines
18
b
and
18
d,
photoresist lines
18
b
and
18
d
block much of etchant flow
20
′. For an etchant ion to reach the bottom of the a sidewall of photoresist line
18
c,
it must either travel towards the sidewall at the perfect angle, or bounce from sidewall to sidewall as shown in FIG.
2
B. The amount of etchant flow
20
′ that reaches the sidewalls of photoresist lines
18
b
and
18
d
are likewise reduced by the close proximity of photoresist line
18
c.
FIG. 2C
illustrates a prior art process of photoresist trimming that has been completed. Because photoresist lines
18
b-d
are located in a dense area of photoresist lines, the top portions of photoresist lines
18
b-d
have been consumed much more rapidly by etchant flow
20
/
20
′ than the bottom portions. Therefore, the sidewalls of photoresist lines
18
b-d
show an undesirable tapering effect, as opposed to critical dimension CD
2
, which is more uniform for photoresist line
18
a.
An ideal etch operation would leave vertical sidewalls in the surface of semiconductor wafer
10
.
Because the top of densely packed photoresist lines
18
b-d
had a higher horizontal etch or trim rate than the bottom, critical dimension CD
3
of photoresist lines
18
b-d
at the top is less than critical dimension CD
4
of photoresist lines
18
b-d
at the bottom. This variation in critical dimensions CD
3
and CD
4
may result in errors during etching of the intermediate layers
15
below photoresist layer
18
. Such errors may in turn cause inconsistencies in the conductive lines formed during fabrication, therefore adversely effecting the speed and response time of the semiconductor device.
Another problem associated with the technique of photoresist trimming is that etchant flow
20
/
20
′ significantly reduces resist budget RB
1
of photoresist lines
18
a-d
shown in
FIG. 2A

Affiliated with

Also associated with

Rating

Methods for reducing profile variation in photoresist trimming does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for reducing profile variation in photoresist trimming, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for reducing profile variation in photoresist trimming will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3147099