Methods for reducing flip chip stress

Details Methods for reducing flip chip stress Methods for reducing flip chip stress

2005-09-13

2005-09-13

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S108000, C438S612000, C438S106000

Reexamination Certificate

active

06943103

ABSTRACT:
Novel methods for reducing shear stress applied to solder bumps on a flip chip. The methods are particularly applicable to reducing temperature-induced shear stress on solder bumps located adjacent to an empty space on a flip chip during high-temperature testing of the chip. According to a first embodiment, the method includes providing an anchoring solder bump in each empty space on the flip chip. The anchoring solder bumps impart additional structural integrity to the flip chip and prevent shear-induced detachment of solder bumps from the flip chip, particularly those solder bumps located adjacent to each anchoring solder bump. According to a second embodiment, the method includes providing an anchoring solder bump in the empty space and then connecting the anchoring solder bump to an adjacent solder bump on the chip using a solder bridge.

REFERENCES:
patent: 6214643 (2001-04-01), Chiu
patent: 6462425 (2002-10-01), Iwasaki et al.
patent: 6479900 (2002-11-01), Shinogi et al.
patent: 6686665 (2004-02-01), Gao et al.

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