Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1996-04-01
2001-08-07
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S296000, C438S224000
Reexamination Certificate
active
06271093
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to methods of manufacture of trench-bounded buried-channel p-type metal oxide semiconductor field effect transistors (p-MOSFETs) as used in dynamic random access memory (DRAM) technologies and, more particularly, to methods for significantly reducing the anomalous buried-channel p-MOSFET sensitivity to device width.
2. Description of the Prior Art
Corner conduction in trench isolated n-channel MOSFETs, as reported by A. Bryant, W. Haensch, S. Geissler, J. Mandelman, D. Poindexter, and M. Steger in “The Current-Carrying Corner Inherent to Trench Isolation”,
IEEE Electron Device Letters,
vol. 14, no. 8, pp. 412-414 (1993), and B. Davari, C. Koburger, T. Furukawa, Y. Taur, W. Noble, J. Warnock, and J. Mauer in “A Variable-Size Shallow Trench Isolation (STI) Technology with Diffused Sidewall Doping for Submicron CMOS”, 1988
IEDM Technical Digest,
pp. 92-95 (1988), could be a significant contributor to standby current in low standby power ultra large scale integration (ULSI) applications. A manifestation of corner conduction is inverse narrow channel effect when the standard current definition of threshold voltage, V
t
,
(
I
V
t
=
40
×
(
W
des
L
des
)
nA
)
,
is applied, where W
des
and L
des
are the design width and design length of the device, respectively. Using V
t
defined by the above equation, inverse narrow channel effect is characterized by a decrease in the magnitude of V
t
as the width of the device decreases.
However, corner conduction in buried-channel p-MOSFETs has not, heretofore, been recognized as a concern. In buried-channel p-MOSFETs, the polarity of the work function difference between the N+ poly gate and the buried p-layer depletes the buried layer of carriers at low gate voltages. Due to the geometrically enhanced field at the silicon corner, it is expected that, when doping is uniform across the device width, the magnitude of V
t
at the corners of these devices is greater than at mid-channel. This leads to a normal channel effect, wherein the magnitude of V
t
increases with decreasing width of the device.
An anomalous (or inverse) narrow channel behavior has been observed in trench-bounded buried-channel p-MOSFETs (as used in contemporary DRAM technologies). Specifically, it has been observed that the magnitude of the threshold voltage, V
t
, drops by approximately 100 mV when going from a device width of 20 &mgr;m down to 2 &mgr;m. The magnitude of V
t
drops more rapidly with further width reduction to approximately 0.4,&mgr;m. For devices narrower than 0.4&mgr;m, the expected normal narrow channel effect is observed, that is, the magnitude of V
t
increases with decreasing width of the device.
If the buried-channel boron dose is decreased to assure that the off-current is less than or equal to the objective over the entire range of design widths, the performance of the widest devices is compromised as a result of the higher than desired V
t
. Consequently, to assure that the narrowest devices meet the off-current objective, the magnitude of the V
t
of the widest devices must be set higher than required by the off-current objective. This results in a performance penalty for the wider devices of typically a 100 mV loss of overdrive.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of minimizing the anomalous channel effect and resulting sensitivity to device width.
To achieve these and other advantages and in accordance with the purpose of the invention embodied and broadly described herein, in one embodiment of the invention, there is provided a method for eliminating the anomalous channel effect including the steps of implanting at least one deep phosphorous n-well; initiating a low temperature anneal using an inert gas; implanting a boron buried-channel; and initiating a gate oxidation. The low temperature annealing step is performed at about 750° C. to about 800° C., for a period of about 10 minutes to about 120 minutes, and utilizes an inert gas, such as, for example, nitrogen or argon. Alternatively, the low temperature anneal may be performed after implanting the boron buried-channel and prior to initiating the gate oxidation.
In another aspect of the invention, there is provided a method for eliminating the anomalous channel effect including the steps of implanting at least one deep phosphorous n-well; implanting a boron buried-channel; and initiating a rapid thermal oxidation (RTO) gate oxidation step. The RTO is performed at about 1025° C. to about 1075° C. for a period of time sufficient to grow the gate oxide. In still another aspect of the invention, the RTO step may be followed by a standard gate oxidation step performed at about 850° C.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4784975 (1988-11-01), Hofmann et al.
patent: 4833096 (1989-05-01), Huang et al.
patent: 5023193 (1991-06-01), Manolin et al.
patent: 5024962 (1991-06-01), Murray et al.
patent: 5091324 (1992-02-01), Hsu et al.
patent: 5294571 (1994-03-01), Fujishiro et al.
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5384279 (1995-01-01), Stolmeijer et al.
patent: 5559050 (1996-09-01), Alsmeier et al.
Bryant et al, “The Current-Carrying Corner Inherent to Trench Isolation”, IEEE Electron Device Lett. vol 14 No. 8, pp. 412-414, Aug. 1993.*
Davari et al, “A Variable Size Shallow Trench Isolation . . . for SubMicron CMOS”, IEDM Technical Digest, pp. 92-95 (1988).*
Wolf et al, “Silicon Processing for the VLSI Era”, vol 1, pp 209-210, 216, 305-307, 1986.*
Chung et al, “An Analytical Threshold Voltage Model of Trench Isolated MOS devices with Nonuniformly Doped Subtrates”, IEEE Transactions on Electron Dev., vol. 39, No. 3, Mar. 1992, pp 614-622.
Alsmeier Johan
Mandelman Jack Allan
Braden Stanton C.
Siemens Aktiengesellschaft
Trinh Michael
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