Methods for message passing decoding using simultaneous...

Details Methods for message passing decoding using simultaneous... Methods for message passing decoding using simultaneous...

2005-10-25

2009-08-04

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S752000, C714S799000, C375S262000, C375S341000

Reexamination Certificate

active

07571375

ABSTRACT:
Respective memory locations are assigned for respective edges linking processing nodes of a decoder comprising a plurality of processing nodes. The decoder is applied to a coded input signal to generate a decoded output signal, wherein edge values are iteratively retrieved from and provided to the memory locations such that multiple ones of the memory locations are simultaneously accessed in a processing node operation. The processing nodes may comprise variable nodes and check nodes and the edges comprise edges linking the variable and check nodes. The invention may be embodied as methods, apparatus and computer program products.

REFERENCES:
patent: 7299397 (2007-11-01), Yokokawa et al.
patent: 7415079 (2008-08-01), Cameron et al.
patent: 2005/0240853 (2005-10-01), Yokokawa et al.
patent: 2005/0278606 (2005-12-01), Richardson et al.
Shokrollah, Amin, “LDPC Codes: An Introduction,” Digital Fountain, Inc., Fremont, CA, Apr. 2, 2003, 34 pages.

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