Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2008-07-15
2008-07-15
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S197000, C438S239000, C438S253000, C438S396000
Reexamination Certificate
active
07399689
ABSTRACT:
Storage nodes for semiconductor memory devices may be fabricated by repeatedly forming conductive and insulating spacers on mold oxide layer pattern sidewalls, to thereby obtain fine line patterns which can increase the surface area of the storage node electrodes. Supporters also may be provided that are configured to support at least one freestanding storage node electrode, to thereby reduce or prevent the storage node electrode from falling or bending towards an adjacent storage node electrode.
REFERENCES:
patent: 5126280 (1992-06-01), Chan et al.
patent: 5554556 (1996-09-01), Ema
patent: 5721154 (1998-02-01), Jeng
patent: 5753419 (1998-05-01), Misium
patent: 5854105 (1998-12-01), Tseng
patent: 5869861 (1999-02-01), Chen
patent: 5913119 (1999-06-01), Lin et al.
patent: 5966600 (1999-10-01), Hong
patent: 6025624 (2000-02-01), Figura
patent: 6063656 (2000-05-01), Clampitt
patent: 6201273 (2001-03-01), Wang et al.
patent: 6380576 (2002-04-01), Tran
patent: 2003/0104710 (2003-06-01), Wang et al.
patent: 42 03 400 (1992-08-01), None
patent: 2 321 771 (1998-08-01), None
patent: 9-116117 (1997-05-01), None
Combined Search and Examination Report for British patent application No. 0500290.2 mailed on May 19, 2005.
Combined Search and Examination Report for British patent application No. 0500291.0 mailed on May 19, 2005.
Combined Search and Examination Report for British patent application No. 0500293.6 mailed on May 18, 2005.
Combined Search and Examination Report for British patent application No. 0500294.4 mailed on May 25, 2005.
Combined Search and Examination Report for British patent application No. 0500295.1 mailed on May 25, 2005.
Combined Search and Examination Report Under Sections 17 and 18(3), UK Application No. GB 0314707.1, Dec. 19, 2003.
Notice to Submit Response, KR Application No. 2002-0037059, Jul. 30, 2004.
Translation of an Official Letter as issued by the German Patent and Trademark Office, Official File No. 103 27 945.8-33, Nov. 2, 2004.
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
Wojciechowicz Edward
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