Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-23
2002-08-06
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S266000, C438S275000, C438S981000
Reexamination Certificate
active
06429073
ABSTRACT:
The copending and commonly assigned patent application No. 09/604,702 entitled “Semiconductor Devices Having a Non-Volatile Memory Transistor”, with Tomoyuki Furuhata and Atsushi Yamazaki listed as inventors, is hereby incorporated by reference in its entirety. The copending and commonly assigned patent application No. 09/602,766 entitled “Non-Volatile Semiconductor Memory Devices”, with Tomoyuki Furuhata and Atsushi Yamazaki listed as inventors, is hereby incorporated by reference in its entirety. Japanese patent application no. 11-177147, filed Jun. 23, 1999, is hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to methods for manufacturing semiconductor devices having a non-volatile memory transistor with a split-gate structure and includes a semiconductor device comprising a plurality of field effect transistors having different operation voltages.
BACKGROUND
In recent years, a mixed-mounting of various circuits has been utilized in view of various demands such as a shortened chip-interface delay, a lowered cost per circuit board, a lowered cost in design and development of a circuit board and the like. A mixed-mounting technology for mounting memory and logic has become one of the important technologies. However, such a mixed-mounting technology presents problems that result in complex processes and higher costs for manufacturing ICs.
SUMMARY
One embodiment of the present invention relates to a method for manufacturing a semiconductor device including a memory region, first, second and third transistor regions including field effect transistors that operate at different voltage levels, wherein the memory region includes a split-gate non-volatile memory transistor, the first transistor region includes a first voltage-type transistor that operates at a first voltage level, the second transistor region includes a second voltage-type transistor that operates at a second voltage level, and the third transistor region includes a third voltage-type transistor that operates at a third voltage level. The method for manufacturing the semiconductor device includes the steps of: (a) forming a gate insulation layer and a floating gate that compose a portion of the non-volatile memory transistor on a silicon substrate in the memory region; (b) forming a first silicon oxide layer on the silicon substrate by a thermal oxidation method, and a second silicon oxide layer by a CVD method; (c) forming a mask layer defining an opening in the first transistor region, and removing the first and the second silicon oxide layers in the first transistor region; (d) forming a silicon oxide layer on the wafer by a thermal oxidation method for gate insulation layers of at least the first voltage-type transistor and second voltage-type transistor; (e) forming a conductive layer and thereafter conducting a patterning to form an intermediate insulation layer and a control gate of the non-volatile memory transistor and a gate insulation layer and a gate electrode for each of the transistors in the transistor regions; and (f) forming an impurity diffusion region that forms a source or a drain by doping an N-type impurity or a P-type impurity in a predetermined region of the silicon substrate. The silicon oxide layer formed in the step (d) forms at least part of a gate insulation layer of the first voltage-type transistor and a gate insulation layer of the second voltage-type transistor.
Another embodiment relates to a method for manufacturing a semiconductor device including forming a gate insulation layer and a floating gate that compose a portion of a non-volatile memory transistor on a silicon substrate in a memory region. A first silicon oxide layer is formed on the substrate by a thermal oxidation method and a second silicon oxide layer by a CVD method. A mask layer defining an opening in a first transistor region is formed, and the first and the second silicon oxide layers in the first transistor region are removed while leaving at least one of the first and second silicon oxide layers remaining in a second transistor region. A silicon oxide layer is formed on the substrate by a thermal oxidation method to form at least a portion of a gate insulation layer of at least the first voltage-type transistor and a second voltage-type transistor. A conductive layer is formed and etched the conductive layer to define an intermediate insulation layer and a control gate of the non-volatile memory transistor and a gate insulation layer and a gate electrode for the first voltage-type transistor and second voltage-type transistor in the transistor region. In addition, an impurity diffusion region that forms a source or a drain is created by doping an N-type impurity or a P-type impurity in a predetermined region of the silicon substrate. The silicon oxide layer formed on the substrate by a thermal oxide method forms at least part of a gate insulation layer of the first voltage-type transistor and a gate insulation layer of the second voltage-type transistor.
Another embodiment relates to method for forming a device including non-volatile semiconductor memory region with a split-gate structure. The method includes forming a source and drain in a substrate. A gate insulation layer is formed, and a floating gate is formed in contact with said gate insulation layer. An intermediate insulation layer is formed in contact with a portion of said floating gate, the intermediate insulation layer being adapted to function as a tunnel insulation layer. The intermediate insulation layer is formed from at least three insulation layers including a first layer that contacts the floating gate, a second layer, and a third layer that contacts a control gate. The control gate is formed in contact with the third layer of the intermediate insulation layer. The intermediate insulation layer and the control gate are formed to have a split-gate structure.
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U.S. Serial No. 09/604,702 (filed Jun. 23, 2000).
U.S. Serial No. 09/602,766 (filed Jun. 23, 2000).
U.S. Serial No. 09/599,477 (filed Jun. 23, 2000).
Furuhata Tomoyuki
Yamazaki Atsushi
Chaudhari Chandra
Konrad Raynes & Victor & Mann LLP
Raynes Alan S.
Seiko Epson Corporation
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