Methods for forming shallow trench isolation

Details Methods for forming shallow trench isolation Methods for forming shallow trench isolation

2006-12-19

2006-12-19

Pham, Thanhha S. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S221000, C438S296000

Reexamination Certificate

active

07151022

ABSTRACT:
Methods of forming a shallow trench isolation structure are disclosed. A disclosed method comprises: depositing pad oxide over a silicon substrate; implanting ions; removing a portion of the pad oxide using an STI pattern; depositing a polysilicon layer; implanting ions to make N+ polysilicon; depositing a bottom anti-reflection coat (BARC) over the polysilicon layer; forming a gate pattern over the BARC; etching the polysilicon layer to make a gate and form a device isolation area; depositing a nitride layer over the gate and the device isolation area; etching the nitride layer; filling the device isolation area with photoresist; forming silicide; and depositing an oxide layer and performing a planarization process.

REFERENCES:
patent: 5830797 (1998-11-01), Cleeves
patent: 6107143 (2000-08-01), Park et al.
patent: 6239003 (2001-05-01), Rao et al.
patent: 6309948 (2001-10-01), Lin et al.
patent: 6417054 (2002-07-01), Zheng et al.
patent: 6432816 (2002-08-01), Kim et al.

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