Methods for forming self-aligned dual stress liners for CMOS...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE27062, C257SE21249, C438S699000

Reexamination Certificate

active

07911001

ABSTRACT:
CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.

REFERENCES:
patent: 5271972 (1993-12-01), Kwok et al.
patent: 2006/0199326 (2006-09-01), Zhu et al.
patent: 2007/0122982 (2007-05-01), Chan et al.
patent: 2008/0150033 (2008-06-01), Greene et al.
patent: 2008/0251851 (2008-10-01), Pan et al.

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