Methods for forming PN junction, one-time programmable...

Details Methods for forming PN junction, one-time programmable... Methods for forming PN junction, one-time programmable...

2005-05-10

2005-05-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S270000, C257S314000

Reexamination Certificate

active

06890819

ABSTRACT:
A method for forming a PN junction is described. A stacked structure consisting of an N-doped (or P-doped) layer, a dielectric layer and a nucleation layer is formed, and then an insulating layer is formed having an opening therein. A P-doped (or N-doped) polysilicon or amorphous silicon layer is filled into the opening, and then annealed to convert into a single-crystal silicon layer. Then, the dielectric layer is broken down to form a PN junction.

REFERENCES:
patent: 5170227 (1992-12-01), Kaneko et al.
patent: 6689644 (2004-02-01), Johnson
patent: 6780711 (2004-08-01), Johnson et al.

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