Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-11-15
2005-11-15
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S625000, C438S641000, C438S674000
Reexamination Certificate
active
06964922
ABSTRACT:
Methods of forming an integrated circuit device can include forming an interlevel dielectric film on an integrated circuit substrate including a conductive portion thereof. The interlevel dielectric film includes a contact hole therein exposing a portion of the conductive portion of the integrated circuit substrate, and the dielectric film includes a trench therein communicating with the contact hole wherein the trench is in a surface of the interlevel dielectric film opposite the integrated circuit substrate. A first metal layer is formed in the contact hole preferentially with respect to formation of the first metal layer on a surface of the interlevel dielectric film opposite the integrated circuit substrate. After preferentially forming the first metal layer in the contact hole, a second metal layer is formed on the surface of the interlevel dielectric film opposite the integrated circuit substrate.
REFERENCES:
patent: 4687552 (1987-08-01), Early et al.
patent: 4902533 (1990-02-01), White et al.
patent: 4963511 (1990-10-01), Smith
patent: 5055423 (1991-10-01), Smith et al.
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5312773 (1994-05-01), Nagashima
patent: 5572072 (1996-11-01), Lee
patent: 5589425 (1996-12-01), Hoshino et al.
patent: 5595937 (1997-01-01), Mikagi
patent: 5604153 (1997-02-01), Tsubouchi et al.
patent: 5633199 (1997-05-01), Fiordalice
patent: 5654245 (1997-08-01), Allen
patent: 5846877 (1998-12-01), Kim
patent: 6001420 (1999-12-01), Mosely
patent: 6080665 (2000-06-01), Chen et al.
patent: 6133147 (2000-10-01), Rhee et al.
patent: 6245655 (2001-06-01), Moslehi
patent: 6376355 (2002-04-01), Yoon et al.
patent: 6432820 (2002-08-01), Lee et al.
patent: 6727176 (2004-04-01), Ngo et al.
patent: 6787460 (2004-09-01), Lee et al.
patent: 2002/0030210 (2002-03-01), Matsui et al.
patent: 0831523 (1998-03-01), None
patent: 07-167340 (1995-04-01), None
patent: 11-186390 (1999-07-01), None
Lee Hyeon-deok
Lee Jong-myeong
Lee Ju-bum
Park In-sun
Jr. Carl Whitehead
Myers Bigel & Sibley & Sajovec
Pham Thanhha
LandOfFree
Methods for forming metal interconnections for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods for forming metal interconnections for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for forming metal interconnections for semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3519404