Methods for forming line patterns in semiconductor substrates

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Including heating

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C430S311000, C430S313000, C430S326000, C430S322000

Reexamination Certificate

active

06803176

ABSTRACT:

FIELD OF THE INVENTION
The invention generally relates to methods for fabricating semiconductor substrates and compositions of matter employed in such methods.
BACKGROUND OF THE INVENTION
In a general process for forming patterns for semiconductor memory devices, after a photoresist pattern is formed on a predetermined target layer to be etched for forming patterns, the target layer is typically etched to a desired pattern using the photoresist pattern as an etching mask. Examples of target layers include silicon layers, insulating layers, or conductive layers. Because of the ever increasing integration of semiconductor devices, it is important to develop lithography technology to form contact holes in the semiconductor devices having smaller opening sizes or finer patterns having narrower spaces. Stated differently, it is believed important to develop design criteria for smaller critical dimensions (CD) in the devices.
A photolithography technique employed for forming fine contact holes uses E-beam lithography with an exposure tool of shorter wavelength and a method that uses a half-tone phase shift mask. In particular, the method employing the exposure tool of shorter wavelength is believed to be disadvantageous in that it is material-intensive and thus relatively expensive to implement. Moreover, a method that utilizes the half-tone phase shift mask is believed to possess limitations in mask manufacturing technology and resolution. Accordingly, it may be difficult to obtain contact holes smaller than 150 nm.
In an attempt to meet the demand for devices with smaller feature sizes, efforts have focused on reducing the opening size or space by applying heat to a photoresist pattern such that the photoresist is able to flow. An example of this technique includes coating a resist layer on a wafer patterned by a photolithography process and then causing the photoresist pattern to flow by heating the resist layer to a temperature that is higher than the glass transition temperature or the softening temperature of the resist layer to reduce the CD of the resultant resist pattern.
Notwithstanding any possible advantages, the above procedure is potentially disadvantageous in that the flow rates in the upper and middle parts of the photoresist pattern are often different. This difference is believed to result in the photoresist pattern having a bowed profile. The bowed profile is believed to be caused by a swelling phenomenon occurring in the middle part of the photoresist pattern. Due to the difficulty in controlling the flow rate of the photoresist pattern by employing conventional resist flow technology, it is often extremely difficult to reduce the CD of the photoresist pattern while maintaining a vertical pattern profile.
U.S. Pat. No. 5,096,802 proposes a photolithographic process for producing a component with reduced feature sizes. The '802 patent proposes controlling the flow rate of a resist through hard baking and deep-UV (DUV) exposure, resulting in the reduced feature sizes. Potential problems may be associated with the '802 patent. For example, the side walls of openings formed in the flowed resist are typically tapered. Accordingly, a target layer underneath the resist pattern is resultantly etched along the tapered side walls during subsequent dry etching. Thus, the upper and lower parts of the openings may have different critical dimensions. In general, the degree of tapering at the side walls of the opening tends to vary among the openings, thereby undesirably causing different critical dimensions to a plurality of holes formed in the target layer over the entire wafer surface. As such, it is typically difficult to obtain a good sidewall profile in a flowed photoresist pattern employing conventional technology.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide methods for forming fine patterns through thermal flowing of photoresist patterns, in which distortion of the profile at the side walls of openings or spaces is minimized, leading to a further reduction in smaller feature size.
It is another object of the present invention to provide compositions suitable for forming fine patterns which go beyond the wavelength limit in a photolithography technology.
In one aspect, the invention provides methods for forming fine patterns in semiconductor substrates. The method first comprises coating a target layer to be etched on a semiconductor substrate with resist compositions. The resist compositions comprise compounds capable of forming a photoresist pattern by a photolithography process, and crosslinking agents. The crosslinking agents are those which are capable of causing partial crosslinking reactions at temperatures equal to or higher than the glass transition temperatures or the softening temperatures of the compounds. The coating steps result in forming resist compound layers comprising the compounds. Thereafter, lithography processes are performed on the resist compound layers to form photoresist patterns of at least one opening having a first width, wherein the target layer is exposed through the first width. Next, the resist compound layers having the photoresist patterns formed therein are heated to temperatures equal to or higher than the glass transition temperatures or the softening temperatures of the compounds, and partial cross-linking reactions in the resist compositions occur. Modified photoresist patterns result having at least one opening having a second width which exposes the target layer, wherein the second width is smaller than the first width. The methods of the invention are believed to be desirable in that the flow rates of the photoresist patterns may be controlled. Moreover, the methods are potentially simpler relative to conventional methods.
In another aspect, the invention provides resist compositions. The resist compositions comprise compounds capable of forming photoresist patterns by photolithography processes, and crosslinking agents. The crosslinking agents are capable of causing partial cross-linking reactions in the resist compositions to form resist compounds at temperatures equal to or higher than the glass transition temperatures or the softening temperatures of the compounds. The crosslinking agents are advantageous in that they may be employed with a number of compounds without adversely affecting the performance of the resist compositions.
In addition to the above, the invention is potentially advantageous in that the distortion of the profile at the side walls of contact holes is minimized, thus allowing for the formation of vertical sidewall profiles. In addition, fine openings which go beyond the wavelength limits in general photolithography technologies can be formed in the photoresist patterns.


REFERENCES:
patent: 4022932 (1977-05-01), Feng
patent: 4259430 (1981-03-01), Kaplan et al.
patent: 5096802 (1992-03-01), Hu
patent: 5510420 (1996-04-01), Dammel et al.
patent: 5858620 (1999-01-01), Ishibashi et al.
patent: 5882843 (1999-03-01), Kudo et al.
patent: 6072006 (2000-06-01), Bantu et al.
patent: 6280897 (2001-08-01), Asakawa et al.
patent: 6358672 (2002-03-01), Jeoung et al.
patent: 6579657 (2003-06-01), Ishibashi et al.
patent: 2002/0028405 (2002-03-01), Kim et al.
patent: 2002/0048723 (2002-04-01), Lee et al.
patent: 1 099 983 (2001-05-01), None
patent: 6-266101 (1994-09-01), None
patent: 6266101 (1994-09-01), None
patent: 7-261392 (1995-10-01), None
patent: 8-211607 (1996-08-01), None
patent: 10-73927 (1998-08-01), None
patent: 1998-080853 (1998-11-01), None
Notice to Submit Response, Korean App. No. 10-1999-0050903, Nov. 10, 2003.
Yamauchi et al.,0.2 &mgr;m Hole Pattern Generation by Critical Dimension Biassing Using Resin Ovarcoat, Jpn. J. Appl. Phys 34:Pt. 1 12B 6615-6621 (Dec., 1995).
Notice to Submit Response, Korean Application No. 10-1999-0050903, Nov. 15, 2001.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Methods for forming line patterns in semiconductor substrates does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for forming line patterns in semiconductor substrates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for forming line patterns in semiconductor substrates will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3265512

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.