METHODS FOR FORMING INTEGRATED CIRCUIT DEVICES THROUGH...

Details METHODS FOR FORMING INTEGRATED CIRCUIT DEVICES THROUGH... METHODS FOR FORMING INTEGRATED CIRCUIT DEVICES THROUGH...

2000-10-31

2003-11-18

Potter, Roy (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S595000

Reexamination Certificate

active

06649490

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2000-13702, filed Mar. 17, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to manufacturing methods for integrated circuit devices and integrated circuit devices formed thereby and, more particularly, to manufacturing methods for integrated circuit devices having a self-aligned contact and integrated circuit devices formed thereby.
BACKGROUND OF THE INVENTION
As integrated circuit devices become more highly integrated and include finer geometries, the width and spacing between interconnections have also been reduced. Self-aligned contact technology has been used to increase alignment margins when using photolithography to form contact holes in predetermined regions between interconnections.
Referring now to
FIG. 1
, a cell array region of a DRAM device may include a plurality of active regions
1
, which are formed in a semiconductor substrate and are repeatedly arranged along the X and Y axes. A plurality of parallel word line patterns
3
cross over the active regions
1
, with one of the active regions
1
′ intersecting two of the word line patterns
3
. A plurality of contact patterns
5
may be used to define self-aligned pad contact holes and are respectively arranged on one side of each of the active regions
1
. Each of the contact patterns
5
may comprise an etching mask (i.e., a photoresist pattern), which may be used to form the self-aligned contact hole.
FIGS. 2-3
,
4
A,
4
B, and
5
-
7
are cross-sectional views of the DRAM device of
FIG. 1
that illustrate a conventional method that may be used to form a self-aligned contact structure. In each of the figures, the reference symbols “A” and “B” denote a memory cell region and a peripheral circuit region, respectively. The memory cell regions A of
FIGS. 2-3
,
4
A, and
5
-
7
are cross-sectional views taken along line I—I of
FIG. 1
, and
FIG. 4B
is a cross-sectional view taken along line II—II of FIG.
1
. To simplify the description, a single NMOS transistor is illustrated in the peripheral circuit region B.
Referring now to
FIG. 2
, a device isolation layer
13
is formed in a predetermined region of a semiconductor substrate
11
to define active regions therein. A gate oxide layer
15
, a conductive layer
17
, a capping insulation layer
19
, and a hard mask layer
21
are sequentially formed on the entire surface of the resultant structure where the device isolation layer
13
is formed. The capping insulation layer
19
and the hard mask layer
21
are typically made from silicon nitride (SiN) and silicon oxide (SiO
2
), respectively. The hard mask layer
21
, the capping insulation layer
19
, and the conductive layer
17
are successively patterned to form a plurality of word line patterns
23
a
on the active regions and the device isolation layer
13
in the memory cell region A and also to form a gate pattern
23
b
on the active region in the peripheral circuit region B. Accordingly, each of the word line patterns
23
a
comprises a word line
17
a
, a capping insulation layer pattern
19
, and a hard mask pattern
21
, which are sequentially stacked as shown. Similarly, each gate pattern
23
b
comprises a gate electrode
17
b
, a capping insulation layer pattern
19
, and a hard mask pattern
21
.
Using the word line patterns
23
b
, the gate pattern
23
b
, and the device isolation layer
13
as an ion implanting mask, N-type impurities are implanted into the active regions to form low concentration impurity regions
24
,
24
a
, and
24
b
. In the memory cell region A, the low concentration impurity region
24
b
formed at a center of the active region corresponds to a common drain region. The low concentration impurity regions
24
a
correspond to source regions.
Referring now to
FIG. 3
, a silicon nitride (SiN) layer is formed on an entire surface of the resultant structure and is then anisotropically etched to form spacers
25
on the sidewalls of the word line patterns
23
a
and the gate pattern
23
b
. Using the gate pattern
23
b
, the spacers
25
, and the device isolation layer
13
as ion implanting masks, N-type impurities are selectively implanted into the active region of the peripheral circuit region B, thereby forming LDD-typed source/drain regions
26
on opposing sides of the gate pattern
23
b
. Typically, the impurities are implanted using a high dose of approximately 1×10
15
ion atoms/cm
2
.
An etch-stop layer
27
is then formed on the entire surface of the resultant structure. Typically, the etch-stop layer
27
comprises an insulator, such as silicon nitride (SiN). Next, an interlayer insulation layer
29
is formed on the entire surface of the resultant structure to fill gap regions between the word line patterns
23
a
as shown in FIG.
3
. Typically, the interlayer insulation layer
29
is formed at a temperature of 800° C. or lower to prevent degradation of the MOS transistors. Specifically, the low concentration impurity regions
24
a
and
24
b
in the memory cell region A and the source/drain regions
26
in the peripheral circuit region B may be re-diffused to reduce the channel length of the transistors when the interlayer insulation layer
29
is made from borophosphosilicate glass (BSPG) that is re-flowed at a high temperature of approximately 850° C. to 950° C. The interlayer insulation layer
29
is, therefore, typically made of a high-density plasma (HDP) oxide that is capable of filling up the gap regions between the word line patterns
23
a
without voids at a temperature of 800° C. or lower. Furthermore, the interlayer insulation layer
29
is preferably more amenable to etching by a given etchant than the etch-stop layer
27
.
When the interlayer insulation layer
29
is made of HDP oxide, however, the power of a high-density plasma apparatus must generally be increased to fill the gap regions between the word line patterns
23
a
. Unfortunately, if the etch-stop layer
27
has a thickness of approximately 200 Å or less, then reacting gas used for the high-density plasma process may infiltrate the etch-stop layer
27
. As a result, the etch-stop layer
27
may tend to lift from the substrate
11
. To suppress this lifting phenomenon, the etch-stop layer
27
may be formed to a thickness of at least 200 Å. But if the thickness of the etch-stop layer
27
is increased, then a lower width of a self-aligned contact hole, which is formed as described hereinafter, may be reduced. Accordingly, it may be difficult to optimize the thickness of the etch-stop layer
27
.
Even though the interlayer insulation layer
29
is planarized, a global step difference S
1
may be generated between the memory cell region A and the peripheral circuit region B as shown in FIG.
3
. Specifically, an upper surface of the interlayer insulation layer
29
in the memory cell region A is lower than that of the peripheral circuit region B. The high-density plasma process, which comprises an alternated and repeated performance of a sputter etching process and a deposition process, may be a cause of the step difference S
1
. The sputter etching process may exhibit a more efficient etching characteristic in a protrusion region than in a plane region. As a result, the interlayer insulation layer
29
may be etched to a more thin thickness in the memory cell region A, which has a relatively high pattern density, than in the peripheral circuit region B.
Referring now to
FIGS. 4A and 4B
, a predetermined region of the interlayer insulation layer
29
in the memory cell region A is anisotropically etched using a photo mask on which the contact patterns
5
, which are shown in
FIG. 1
, are drawn. The etch-stop layer
27
is then etched to form self-aligned pad contact holes H
1
and H
2
, which expose the source regions
24
a
and the common drain region
24
b
in the memory cell region A. After etching the etch-stop layer
27
to form the pad contact holes H
1
and H
2
, some etch-st

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