Methods for forming high-performing dual-damascene interconnect

Details Methods for forming high-performing dual-damascene interconnect Methods for forming high-performing dual-damascene interconnect

1998-09-25

2000-06-06

Fahmy, Wael

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438637, 438622, 438631, 438633, 438645, H01L 214763

Patent

active

060718099

ABSTRACT:
Dual damascene methods and structures are provided for IC interconnects which use a dual-damascene process incorporating a low-k dielectric material, high conductivity metal, and an improved hard mask scheme. A pair of hard masks are employed: a silicon dioxide layer and a silicon nitride layer, wherein the silicon dioxide layer acts to protect the silicon nitride layer during dual damascene etch processing, but is subsequently sacrificed during CMP, allowing the silicon nitride layer to act as a the CMP hard mask. In this way, delamination of the low-k material is prevented, and any copper-contaminated silicon dioxide material is removed.

REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 5663101 (1997-09-01), Cronin
patent: 5736457 (1998-04-01), Zhao
patent: 5741626 (1998-04-01), Jain et al.
patent: 5821168 (1998-10-01), Jain

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