Methods for forming fine pattern of semiconductor device

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S719000, C438S725000, C438S156000

Reexamination Certificate

active

10462448

ABSTRACT:
Provided is a method for forming a fine pattern of a semiconductor device by controlling the amount of flow of a resist pattern, including forming a resist pattern having a predetermined pattern distance on a material layer to be etched, forming a flow control barrier layer on the resist pattern to control the amount of flow during a subsequent resist flow process and to make the profile of the flowed pattern be vertical, optionally forming the flow control barrier layer by coating a material including a water-soluble high-molecular material and a crosslinking agent on the resist pattern, mixing and baking the coated material layer, and processing the resultant structure using deionized water, carrying out the flow resist process to form a hyperfine pattern and etching the lower material layer, and thereby forming fine patterns having the shape of contact holes or lines and spaces to have a critical dimension of about 100 nm or less, even with use of a KrF resist.

REFERENCES:
patent: 6348301 (2002-02-01), Lin
patent: 6486058 (2002-11-01), Chun
patent: 6489085 (2002-12-01), Huang et al.
patent: 6579657 (2003-06-01), Ishibashi et al.
patent: 6740473 (2004-05-01), Lin et al.
patent: 1998-0011726 (1998-04-01), None
patent: 1020010076552 (2001-08-01), None
Wolf et al., Silicon Processing for the VLSI Era, 1986, Lattice Press, vol. 1, pp. 453-454.

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