Methods for forming co-planar wafer-scale chip packages

Details Methods for forming co-planar wafer-scale chip packages Methods for forming co-planar wafer-scale chip packages

2004-11-20

2008-07-29

Coleman, W. David (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

C438S464000, C257SE21122

Reexamination Certificate

active

07405108

ABSTRACT:
Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

REFERENCES:
patent: 4907062 (1990-03-01), Fukushima
patent: 5091331 (1992-02-01), Delgado et al.
patent: 5324687 (1994-06-01), Wojnarowski
patent: 6001740 (1999-12-01), Varian et al.
patent: 6177299 (2001-01-01), Hsu et al.
patent: 6555906 (2003-04-01), Towle et al.
patent: 6964881 (2005-11-01), Chua et al.
patent: 7005319 (2006-02-01), Chen et al.
patent: 2003/0205796 (2003-11-01), Hakey et al.
patent: 2003/0216010 (2003-11-01), Atlas
patent: 2005/0116337 (2005-06-01), Chua et al.
patent: 2006/0035443 (2006-02-01), Hsu et al.

Affiliated with

Also associated with

Rating

Methods for forming co-planar wafer-scale chip packages does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for forming co-planar wafer-scale chip packages, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for forming co-planar wafer-scale chip packages will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3962761