Methods for fabricating transistor gate structures

Details Methods for fabricating transistor gate structures Methods for fabricating transistor gate structures

2003-06-16

2004-09-07

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S682000

Reexamination Certificate

active

06787425

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor device manufacturing and more particularly to methods for fabrication of transistor gate structures.
BACKGROUND OF THE INVENTION
MOS transistors are found in many modern semiconductor products where switching and/or amplification functions are needed. Many manufacturing processes and techniques have been developed for fabricating MOS devices in semiconductor substrate materials such as silicon and the like. In recent years, the size of transistors and other components have steadily decreased to submicron levels in order to facilitate higher device densities in semiconductor products, wherein current design targets involve feature sizes in the sub-100 nm range. At the same time, many new applications have created a need to operate transistors and other semiconductor devices at lower power and voltage levels. In addition, switching speed requirements of MOS transistors continue to increase in order to facilitate faster and improved product performance. Accordingly, efforts continue to be made to design semiconductor devices, such as MOSFET transistors, which occupy less physical space, consume less power, and operate at higher switching speeds and at lower voltages.
MOS transistors include a conductive gate overlying a channel region of a semiconductor substrate with a thin gate dielectric, typically oxide, therebetween. Source and drain regions of the substrate (sometimes referred to as junction regions) are doped with impurities on opposite sides of the channel, wherein the source/drain regions of NMOS devices are doped with n-type impurities (e.g., As, Sb, P, etc.) and PMOS devices are doped using p-type impurities (e.g., B, Ga, In, etc.). The source and drain dopants are typically implanted into the silicon substrate using ion implantation systems, wherein the dosage and energy of the implanted ions may be varied depending upon the desired dopant concentration, depth, and profile. The ion dosage generally controls the concentration of implanted ions for a given semiconductor material, and the energy level of the beam ions determines the distance of penetration or depth of the implanted ions (e.g., the junction depth).
Electrical connections are typically made to transistor gate structures and source/drain regions of the substrate by forming silicide structures thereover. Sidewall spacers are typically formed along the lateral sidewalls of the gate structures to prevent shorting of the gate silicide to the source/drain silicide. Interlayer or interlevel dielectric (ILD) material is then formed over the wafer, through which vias are etched and filled with conductive material (e.g., tungsten, copper, or the like) to provide electrical contact connections to the gate and source/drain silicide structures. Interconnection of the various devices in the wafer is then accomplished by forming: a multi-level interconnect network in dielectric layers formed over the electrical devices, by which the device active elements are connected to other devices to create the desired circuits in the finished integrated circuit. In forming the silicide structures and subsequent conductive contacts, it is desirable to minimize the likelihood of short-circuits between the source/drain and the transistor gate. Accordingly, there is a need for improved transistor fabrication techniques by which process margins for contact formation can be maximized to reduce the probability of such short circuits in the manufacture of semiconductor products.
SUMMARY OF THE INVENTION
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented hereinafter.
The inventors have appreciated that forming silicide over sub-100 nm gate structures sometimes results in volume, expansion of the resulting conductive suicide beyond the sidewall spacers, referred to herein as silicide “bread-loafing”. This situation can reduce the process margins for forming source/drain contacts to avoid shorting to the gate. In addition, where the gate contact material is polysilicon, certain fabrication process flows provide for growth of epitaxial silicon over the gate polysilicon prior to silicidation of the gate contact. In this situation, the inventors have found that the epitaxial silicon itself may form above and laterally outward from the tops of the gate sidewall spacers, referred to hereinafter as polysilicon “mushrooming”. The outward growth of the epitaxial silicon reduces the source/drain contact formation process margins, and subsequent silicide bread-loafing further worsens the situation. The invention provides transistor fabrication techniques which may be employed to combat silicide bread-loafing and polysilicon mushrooming effects during the manufacture of semiconductor products by providing a recess at the top of a patterned gate structure in which silicide and/or epitaxial silicon is formed. This, in turn, advantageously mitigates or avoids the process margin reduction seen in prior fabrication processes, and may thus reduce the likelihood of source/drain contacts shorting to the transistor gate and facilitate scaling of feature sizes in semiconductor products.
In accordance with the present invention, a method is provided for fabricating MOS transistors, in which a gate dielectric layer and a polysilicon or other gate contact layer are formed over a channel region of a semiconductor body. The method provides for formation of a sacrificial material, such as silicon germanium (SiGe) over the polysilicon layer, patterning of the sacrificial material and the polysilicon layer to define a gate structure, and formation of sidewall spacers along the gate structure sidewalls. The sacrificial material is then removed from the patterned gate structure, thus exposing the polysilicon gate contact and providing a recess in the gate structure between upper ends of the sidewall spacers. Thereafter, an epitaxial silicon may be formed in the recess, and the gate may then be implanted with dopants. A suicide is then formed over the epitaxial silicon or the polysilicon within the recess, where the thickness of the sacrificial material may be formed to correspond to the silicide thickness or to the combined thicknesses of the epitaxial silicon material and the silicide structure. In this way, the formation of the silicide structure substantially fills the recess of the gate structure without bread-loafing.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.


REFERENCES:
patent: 5902125 (1999-05-01), Wu
patent: 6265272 (2001-07-01), Chen
patent: 6335251 (2002-01-01), Miyano et al.
patent: 6444529 (2002-09-01), Ahmad et al.
patent: 6518155 (2003-02-01), Chau et al.

Affiliated with

Also associated with

Rating

Methods for fabricating transistor gate structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for fabricating transistor gate structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for fabricating transistor gate structures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3266148