Methods for fabricating stressed MOS devices

Details Methods for fabricating stressed MOS devices Methods for fabricating stressed MOS devices

2011-07-12

2011-07-12

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S216000, C438S231000, C438S299000, C438S300000, C257S335000, C257S341000, C257S369000, C257S374000, C257SE21639

Reexamination Certificate

active

07977180

ABSTRACT:
Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are implanted into the polycrystalline silicon gate electrode layer to form a P-type implanted region and a first polycrystalline silicon gate electrode is formed overlying the P-well region. Recesses are etched into the P-well region using the first polycrystalline silicon gate electrode as an etch mask. The step of etching is performed by exposing the silicon substrate to tetramethylammonium hydroxide. A tensile stress-inducing material is formed within the recesses.

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patent: 2006/0202278 (2006-09-01), Shima et al.
patent: 2007/0052043 (2007-03-01), Cha et al.
patent: 2008/0142838 (2008-06-01), Ohta et al.

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