Methods for fabricating microelectronic device interconnects...

Details Methods for fabricating microelectronic device interconnects... Methods for fabricating microelectronic device interconnects...

2000-04-19

2002-02-12

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S584000, C438S618000, C438S622000

Reexamination Certificate

active

06346473

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to microelectronic devices and fabrication methods therefor, more particularly, to interconnects for microelectronic devices and fabrication methods therefor.
BACKGROUND OF THE INVENTION
As the integration level of microelectronic devices increases, interconnects for these devices, which can significantly influence the speed, product yield, and reliability of the device, increasingly employ a multi-layered structure. Conventional techniques for forming such a multilevel interconnect typically employ a planarization process to increase resolution and depth-of-focus in photolithography. In particular, a planarization process using spun-on-glass (SOG) has been widely applied because of advantages of low cost, process simplification, no need for a poisonous gas, and tendency to form a low defect density when compared with other planarization processes.
In a typical planarization process using SOG, liquid SOG is coated on a semiconductor substrate to form an SOG layer, which is then baked in a range of 150-400° C. to remove solvents and moisture. During this process, the SOG is condensed and tensile stresses may develop in the SOG layer, producing fine cracks in the SOG layer, especially in SOG layers having thicknesses of 3,000 Å or more.
The SOG layer tends to form more thickly in areas adjacent to the edge of a semiconductor wafer. As thin films are continuously deposited, very large steps, that is, steps of 2.0 &mgr;m or more, may be formed between the edge of a semiconductor wafer and adjacent areas for forming devices thereon, as the edge of the semiconductor wafer typically is not exposed in photolithography. Consequently, an SOG layer formed in this area may have a thickness of 2.0 &mgr;m or more, and thus may be more susceptible to cracks.
To reduce formation of such fine cracks, an organic SOG containing an organic group such as a methyl (CH
3
−) group or a phenyl (C
6
H
5
−) group is usually used instead of an inorganic SOG which lacks such a group. However, organic SOG typically is more volatile and harder to contain than inorganic SOG.
FIGS. 1-3
are cross-sectional views showing a conventional method for forming a multilevel interconnects in a semiconductor device. Referring to
FIG. 1
, a conductive pattern
30
is formed on a semiconductor substrate
10
having a first insulation layer
20
formed thereon. A second insulation layer
40
is then formed to a uniform thickness on the overall surface of the resultant structure, covering the conductive pattern
30
. Steps are typically formed in the second insulation layer pattern
40
due to the presence of the conductive pattern
30
. A first area H is defined where the height between the surface of the semiconductor substrate
10
and the surface of the second insulation layer
40
is relatively high, and a second area L is defined where the height is relatively low.
Subsequently, lower conductive patterns
50
a
,
50
b
, and
50
c
are formed on the second insulation layer
40
. Here, the first lower conductive pattern
50
a
is formed in the first area H, and the second and third lower conductive patterns
50
b
and
50
c
are formed in the second area L. The second lower conductive pattern
50
b
is positioned between the first and third lower conductive patterns
50
a
and
50
c.
A third insulation layer
60
is formed, covering lower conductive patterns
50
a
,
50
b
, and
50
c
. An SOG layer
70
is then formed by coating an inorganic or organic SOG on the third insulation layer
60
using a spin-on process. Here, SOG typically flows into the second area L due to its high fluidity, making the SOG layer thicker in the second area L than in the first area H. Therefore, the SOG layer
70
tends to be relatively planar, and is thickest in a portion A of the area L adjacent to the first area H.
The SOG layer
70
is then baked at between 150 and 400° C. to remove solvents and moisture from the SOG layer
70
. During this baking process, the thicker portion A of the SOG layer
70
tends to be more susceptible to fine cracks. Though fine cracks can be reduced by forming the SOG layer
70
of an organic SOG instead of an inorganic SOG, it is difficult to efficiently reduce the stress-induced fine cracks due to the thickness of the portion A of the SOG layer
70
.
Referring to
FIG. 2
, a planarization layer
70
a
is formed by uniformly etching back the overall surface of the SOG layer
70
to a predetermined depth until the third insulation layer
60
on the third lower conductive pattern
50
c
is exposed. The reason for etch-back is to further planarize the surface of the SOG layer
70
and reduce the aspect ratio of a later-formed via hole.
Because the SOG layer
70
is thinner on the first lower conductive pattern
50
a
than on the third lower conductive pattern
50
c
, the third insulation layer
60
on the first lower conductive pattern
50
a
is typically exposed. However, because the SOG layer
70
is thicker on the second lower conductive pattern
50
b
than on the third conductive pattern
50
c
, the third insulation layer
60
on the second lower conductive pattern
50
b
typically is not exposed.
A fourth insulation layer
80
is then formed on the surface of the resultant structure. A photoresist layer pattern
90
a
is formed on the fourth insulation layer
80
to expose the fourth insulation layer
80
on the second and third lower conductive patterns
50
b
and
50
c
. Referring to
FIG. 3
, a fourth insulation layer pattern
80
a
having via holes for exposing the second and third lower conductive patterns
50
b
and
50
c
, respectively, a planarization layer pattern
70
b
, and a third insulation layer pattern
60
a
are formed by sequentially etching the fourth insulation layer
80
, the planarization layer
70
a
, and the third insulation layer
60
, using the photosensitive layer pattern
90
a
as an etching mask.
To simultaneously expose the second and third lower conductive patterns
50
b
and
50
c
, the upper portion of the second lower conductive pattern
50
b
typically is further etched. When etching is performed for the purpose of exposing the third lower conductive pattern
50
c
, the second lower conductive pattern
50
b
may not be exposed. On the other hand, when etching is performed for the purpose of exposing the second lower conductive pattern
50
b
, the upper portion of the third conductive pattern
50
c
may be over-etched, and the via hole for exposing the third lower conductive pattern
50
c
may become wider, potentially resulting in formation of a connection between the via hole and an adjacent via hole (not shown), or exposing another conductive layer which should not be exposed.
First and second upper conductive patterns
100
a
and
100
b
are then formed on the fourth insulation layer pattern
80
a
to make contact with the second and third lower conductive patterns
50
b
and
50
c
through the via holes, respectively.
If the SOG layer
70
is formed of an organic SOG to reduce fine cracks on the planarization layer
70
a
in area A, high molecular weight substances may be produced during forming the via hole for exposing the second lower conductive pattern
50
b
. These high molecular weight substances may locally accumulate on the second lower conductive pattern
50
b
, thereby increasing contact resistance. High molecular weight substances typically are formed because silicon (Si) and oxygen (O) components of the organic SOG are vaporized as silicon fluoride (SiF
4
) and carbon dioxide (CO
2
) during etching by a carbon fluoride (CF
4
or C
2
F
6
) etching gas, whereas organic components of the organic SOG are not removed.
According to the conventional method described above, the SOG planarization layer
70
a
in area A is susceptible to fine cracks. The second lower conductive pattern
50
b
may not make contact with the first upper conductive pattern
100
a
. In addition, the via hole exposing the third lower conductive pattern
50
c
may be larger than intended.
SUMMARY OF THE INVENTION
In l

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