Methods for fabricating light emitting devices having...

Details Methods for fabricating light emitting devices having... Methods for fabricating light emitting devices having...

2001-08-06

2002-07-16

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

C438S046000, C438S459000, C438S977000

Reexamination Certificate

active

06420199

ABSTRACT:

FIELD OF INVENTION
The invention is directed towards the field of light emission particularly towards providing high quality reflective surfaces to both sides of an Al
x
Ga
y
In
z
N device,
BACKGROUND
A vertical cavity optoelectronic structure consists of an active region that is formed by light emitting layer interposing confining layers that may be doped, un-doped, or contain a p-n junction. The structure also contains at least one reflective mirror that forms a Fabry-Perot cavity in the direction normal to the light emitting layers. Fabricating a vertical cavity optoelectronic structure in the GaN/Al
x
Ga
y
In
z
N/Al
x
Ga
1−x
N (where x+y+z=1 in Al
x
Ga
y
In
z
N and where x≦1 in Al
x
Ga
1−x
N) material systems poses challenges that set it apart from other III-V material systems. It is difficult to grow Al
x
Ga
y
In
z
N structures with high optical quality. Current spreading is a major concern for Al
x
Ga
y
In
z
N devices. Lateral current spreading in the p-type material is ~30 times less than that in the n-type material. Furthermore, the low thermal conductivity of many of the substrates adds complexity to the device design, since the devices should be mounted junction down for optimal heat sinking.
One vertical cavity optoelectronic structure, e.g. a vertical cavity surface emitting laser (VCSEL), requires high quality mirrors, e.g. 99.5% reflectivity. One method to achieve high quality mirrors is through semiconductor growth techniques. To reach the high reflectivity required of distributed Bragg reflectors (DBRs) suitable for VCSELs (>99%), there are serious material issues for the growth of semiconductor Al
x
Ga
y
In
z
N DBRs, including cracking and electrical conductivity. These mirrors require many periods/layers of alternating indium aluminum gallium nitride compositions (Al
x
Ga
y
In
z
N/Al
x
.Ga
y
.In
z
.N). Dielectric DBRs (D-DBR), in contrast to semiconductor DBRs, are relatively straightforward to make with reflectivities in excess of 99% in the spectral range spanned by the Al
x
Ga
y
In
z
N system. These mirrors are typically deposited by evaporation or sputter techniques, but MBE (molecular beam epitaxial) and MOCVD (metal-organic chemical vapor deposition) can also be employed. However, only one side of the active region can be accessed for D-DBR deposition unless the growth substrate is removed. Producing an Al
x
Ga
y
In
z
N vertical cavity optoelectronic structure would be significantly easier if it was possible to bond and/or deposit D-DBRs on both sides of a Al
x
Ga
y
In
z
N active region.
Wafer bonding can be divided into two basic categories: direct wafer bonding, and metallic wafer bonding. In direct wafer bonding, the two wafers are fused together via mass transport at the bonding interface. Direct wafer bonding can be performed between any combination of semiconductor, oxide, and dielectric materials. It is usually done at high temperature (>400° C.) and under uniaxial pressure. One suitable direct wafer bonding technique is described by Kish, et al., in U.S. Pat. No. 5,502,316. In metallic wafer bonding, a metallic layer is deposited between the two bonding substrates to cause them to adhere. One example of metallic bonding, disclosed by Yablonovitch, et al. in Applied Physics Letters, vol. 56, pp. 2419-2421, 1990, is flip-chip bonding, a technique used in the micro- and optoelectronics industry to attach a device upside down onto a substrate. Since flip-chip bonding is used to improve the heat sinking of a device, removal of the substrate depends upon the device structure and conventionally the only requirements of the metallic bonding layer are that it be electrically conductive and mechanically robust.
In “Low threshold, wafer fused long wavelength vertical cavity lasers”, Applied Physics Letters, Vol. 64, No. 12, 1994, pp1463-1465, Dudley, et al. taught direct wafer bonding of AlAs/GaAs semiconductor DBRs to one side of a vertical cavity structure while in “Room-Temperature Continuous-Wave Operation of 1.54-&mgr;m Vertical-Cavity Lasers,” IEEE Photonics Technology Letters, Vol. 7, No. 11, November 1995, Babic, et al. taught direct wafer bonded semiconductor DBRs to both sides of an InGaAsP VCSEL to use the large refractive index variations between AlAs/GaAs. As will be described, wafer bonding D-DBRs to Al
x
Ga
y
In
z
N is significantly more complicated than semiconductor to semiconductor wafer bonding, and was not known previously in the art.
In “Dielectrically-Bonded Long Wavelength Vertical Cavity Laser on GaAs Substrates Using Strain-Compensated Multiple Quantum Wells,” IEEE Photonics Technology Letters, Vol. 5, No. 12, December 1994, Chua et al. disclosed AlAs/GaAs semiconductor DBRs attached to an InGaAsP laser by means of a spin-on glass layer. Spin-on glass is not a suitable material for bonding in a VCSEL between the active layers and the DBR because it is difficult to control the precise thickness of spin on glass, and hence the critical layer control needed for a VCSEL cavity is lost. Furthermore, the properties of the glass may be inhomogeneous, causing scattering and other losses in the cavity.
Optical mirror growth of Al
x
Ga
1−x
N/GaN pairs of semiconductor DBR mirrors with reflectivities adequate for VCSELs, e.g. >99%, is difficult. Referring to
FIG. 1
, theoretical calculations of reflectivity suggest that to achieve the required high reflectivity, a high index contrast is required that can only be provided by increasing the Al composition of the low-index Al
x
Ga
1−x
N layer and/or by including more layer periods (material properties taken from Ambacher et al., MRS Internet Journal of Nitride Semiconductor Research, 2(22) 1997). Either of these approaches introduces serious challenges. If current will be conducted through the DBR layers, it is important that the DBRs be conductive. To be sufficiently conductive, the Al
x
Ga
1−x
N layer must be adequately doped. Electrical conductivity is insufficient unless the Al composition is reduced to below approximately 50% for Si (n-type) doping and to below approximately 20% for Mg (p-type) doping. However, as shown in
FIG. 1
, the number of layer periods needed to achieve sufficient reflectivity using lower Al composition layers requires a large total thickness of Al
x
Ga
1−x
N material, increasing the risk of epitaxial layer cracking (due to the relatively large lattice mismatch between AlN and GaN) and reducing compositional control. Indeed, the Al
0.30
Ga
0.70
N/GaN stack of
FIG. 1
is already ~2.5 &mgr;m thick and is far from sufficiently reflective for a VCSEL. Thus, a high reflectivity DBR based on this layer pair requires a total thickness significantly greater than 2.5 &mgr;m and would be difficult to grow reliably given the mismatch between AlN and GaN growth conditions and material properties. Even though the cracking is not as great of an issue if the layers are un-doped, compositional control and the AlN/GaN growth temperatures still pose great challenges to growing high reflectivity DBRs. Hence, even in applications where the DBRs do not have to conduct current, semiconductor mirror stacks with reflectivities >99% in the Al
x
Ga
y
In
z
N material system have not been demonstrated. For this reason, dielectric-based DBR mirrors are preferred.
SUMMARY
At least one mirror stack, e.g. a dielectric distributed Bragg reflector (D-DBR) or composite D-DBR/semiconductor DBR interposes a Al
x
Ga
y
In
z
N active region and a host substrate. A wafer bond interface is positioned somewhere between the host substrate and the active region. An optional intermediate bonding layer is adjacent the wafer bond interface to accommodate strain and thermal coefficient mismatch at the wafer bond interface. An optional mirror stack is positioned adjacent the Al
x
Ga
y
In
z
N active region. Either the host substrate or intermediate bonding layer is selected for compliancy.
One embodiment of the aforementioned invention consists of a device having the wafer bond interface positioned adjacent the Al
x
Ga
y
In
z
N active region, the

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