Methods for fabricating dual bit flash memory devices

Details Methods for fabricating dual bit flash memory devices Methods for fabricating dual bit flash memory devices

2011-01-11

2011-01-11

Monbleau, Davienne (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21210, C257SE21645

Reexamination Certificate

active

07867848

ABSTRACT:
Methods for fabricating dual bit memory devices are provided. In an exemplary embodiment of the invention, a method for fabricating a dual bit memory device comprises forming a charge trapping layer overlying a substrate and etching an isolation opening through the charge trapping layer. An oxide layer is formed overlying the charge trapping layer and within the isolation opening. A control gate is fabricated overlying the isolation opening and portions of the charge trapping layer adjacent to the isolation opening. The oxide layer and the charge trapping layer are etched using the control gate as an etch mask and impurity dopants are implanted into the substrate using the control gate as an implantation mask.

REFERENCES:
patent: 6524913 (2003-02-01), Lin et al.
patent: 6639271 (2003-10-01), Zheng et al.
patent: 6861307 (2005-03-01), Zheng et al.
patent: 6917068 (2005-07-01), Krivokapic
patent: 6962849 (2005-11-01), Kamal et al.
patent: 2004/0021172 (2004-02-01), Zheng et al.
patent: 2006/0240635 (2006-10-01), Shiraiwa et al.

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