Methods for fabricating a stressed MOS device

Details Methods for fabricating a stressed MOS device Methods for fabricating a stressed MOS device

2005-08-16

2008-12-09

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S592000

Reexamination Certificate

active

07462524

ABSTRACT:
Methods are provided for fabricating a stressed MOS device. One method comprises the steps of providing a substrate of a monocrystalline semiconductor material having a first lattice constant, and forming a conductive gate electrode overlying the substrate, the gate electrode having opposing sides and having a thickness. Sidewall spacers are formed on the opposing sides of the gate electrode and trenches are etched in the semiconductor substrate in alignment with the sidewall spacers. A portion of the thickness of the conductive gate electrode is also etched to leave a remaining portion of the conductive gate electrode. A stress inducing layer of material is grown on the remaining portion of the conductive gate electrode and filling the trenches, the stress inducing layer of material having a second lattice constant different than the first lattice constant.

REFERENCES:
patent: 6124189 (2000-09-01), Watanabe et al.
patent: 6406973 (2002-06-01), Lee
patent: 7238580 (2007-07-01), Orlowski et al.
patent: 7265400 (2007-09-01), Matsuda

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