Methods for fabricating a stress enhanced MOS circuit

Details Methods for fabricating a stress enhanced MOS circuit Methods for fabricating a stress enhanced MOS circuit

2006-08-22

2008-08-26

Smith, Matthew S. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S585000, C438S285000, C438S300000, C257SE21317, C257SE21444, C257SE21621, C257SE21633, C257SE21634

Reexamination Certificate

active

07416931

ABSTRACT:
Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel region in the semiconductor substrate so that the stressed dummy gate induces a stress in the channel region. Regions of the semiconductor substrate adjacent the channel are processed to maintain the stress to the channel region and the stressed dummy gate electrode is replaced with a permanent gate electrode.

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