Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-12-20
2010-02-23
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S288000, C257SE21679
Reexamination Certificate
active
07666739
ABSTRACT:
Methods are provided for fabricating a split charge storage node semiconductor memory device. In accordance with one embodiment the method comprises the steps of forming a gate insulator layer having a first physical thickness and a first effective oxide thickness on a semiconductor substrate and forming a control gate electrode having a first edge and a second edge overlying the gate insulator layer. The gate insulator layer is etched to form first and second undercut regions at the edges of the control gate electrode, the first and second undercut region each exposing a portion of the semiconductor substrate and an underside portion of the control gate electrode. First and second charge storage nodes are formed in the undercut regions, each of the charge storage nodes comprising an oxide-storage material-oxide structure having a physical thickness substantially equal to the first physical thickness and an effective oxide thickness less than the first effective oxide thickness.
REFERENCES:
patent: 6750103 (2004-06-01), Higashitani et al.
patent: 7432156 (2008-10-01), Lee et al.
Chang Kuo-Tung
Kinoshita Hiroyuki
Lee Chung-ho
Melik-Martirosian Ashot
Rinji Sugimo
Chaudhari Chandra
Spansion LLC
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