Methods for fabricating a memory device including a dual bit...

Details Methods for fabricating a memory device including a dual bit... Methods for fabricating a memory device including a dual bit...

2006-12-20

2009-12-22

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S593000, C438S508000, C438S508000, C257S315000, C257S320000

Reexamination Certificate

active

07635627

ABSTRACT:
Methods are provided for fabricating a memory device comprising a dual bit memory cell. The method comprises, in accordance with one embodiment of the invention, forming a gate dielectric layer and a central gate electrode overlying the gate dielectric layer at a surface of a semiconductor substrate. First and second memory storage nodes are formed adjacent the sides of the gate dielectric layer, each of the first and second storage nodes comprising a first dielectric layer and a charge storage layer, the first dielectric layer formed independently of the step of forming the gate dielectric layer. A first control gate is formed overlying the first memory storage node and a second control gate is formed overlying the second memory storage node. A conductive layer is deposited and patterned to form a word line coupled to the central gate electrode, the first control gate, and the second control gate.

REFERENCES:
patent: 6768160 (2004-07-01), Li et al.
patent: 2005/0029577 (2005-02-01), Nishizaka et al.

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