Methods for fabricating a CMOS device including silicide...

Details Methods for fabricating a CMOS device including silicide... Methods for fabricating a CMOS device including silicide...

2008-03-25

2008-03-25

Le, Thao X. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S306000, C438S682000, C257S384000, C257SE21634, C257SE21619

Reexamination Certificate

active

11207265

ABSTRACT:
Methods are provided for fabricating a CMOS device having a silicon substrate including a first N-type region and a second P-type region. The method includes the steps of forming a first gate electrode overlying the first N-type region and a second gate electrode overlying the second P-type region. P-type source and drain regions are ion implanted into the first N-type region, and N-type source and drain regions are ion implanted into the second P-type region. First silicide regions, spaced apart from the first gate electrode by a first distance, are formed contacting the P-type source and drain regions, and second silicide regions, spaced apart from the second gate electrode by a second distance less than the first distance, are formed contacting the N-type source and drain regions.

REFERENCES:
patent: 6214673 (2001-04-01), Grebs et al.
patent: 6853048 (2005-02-01), Wylie
patent: 6869866 (2005-03-01), Chidambarrao et al.
patent: 2002/0081827 (2002-06-01), Hamanaka
patent: 2004/0056304 (2004-03-01), Ahmed et al.

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