Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-07-01
2008-07-01
Chase, Shelly (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000
Reexamination Certificate
active
07395468
ABSTRACT:
The present invention is directed to a method for debugging scan testing failures of integrated circuits. The method includes identifying a bad scan path among a set of scan paths and segmenting the bad scan path into two segments. Once the bad scan path is segmented into two segments, scan tests are run to determine whether the source of errors is near the segment point. If the number of errors generated is below a threshold, the specific location of errors can be identified by tracing the errors either manually or automatically through an automated testing unit. If the source of errors is not near the segment point, the segment point is shifted based on an analysis of the errors on the good and bad scan paths. Additional scan tests are then run and the method repeated until the location of the source of errors is found.
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U.S. Appl. No. 10/950,637, entitled “Methods and Computer Program Products for Debugging clock-Related Scan Testing Failures of Integrated Circuits,” filed Sep. 28, 2004.
Office Action for U.S. Appl. No. 10/950,637, dated Sep. 27, 2006, 9 pages.
Office Action for U.S. Appl. No. 10/950,637, dated Apr. 11, 2007, 6 pages.
Broadcom Corporation
Chase Shelly
Radosevich Steven D
Sterne Kessler Goldstein & Fox P.L.L.C.
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