Methods for analyzing scan chains, and for determining...

Details Methods for analyzing scan chains, and for determining... Methods for analyzing scan chains, and for determining...

2011-08-30

2011-08-30

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S728000, C714S729000, C714S730000, C714S731000

Reexamination Certificate

active

08010856

ABSTRACT:
In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined.

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