Methods and systems for semiconductor defect detection

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S733000, C714S819000, C714S723000

Reexamination Certificate

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11203236

ABSTRACT:
A method for semiconductor defect detection, applied to a wafer test in a semiconductor process. A defect test is implemented for generating redundant information. an abnormal test implemented for generating a first FBM. The redundant information is converted to a second FBM. The first and second FBMs are compared, thereby generating a third FBM according to comparison results.

REFERENCES:
patent: 4266294 (1981-05-01), Daughton et al.
patent: 5760892 (1998-06-01), Koyama
patent: 5828778 (1998-10-01), Hagi et al.
patent: 6477685 (2002-11-01), Lovelace
patent: 7137055 (2006-11-01), Hirano et al.

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