Methods and structures for planar and multiple-gate...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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C438S153000, C438S154000, C438S164000, C257S347000

Reexamination Certificate

active

07851276

ABSTRACT:
A semiconductor device includes an insulator layer, a semiconductor layer, a first transistor, and a second transistor. The semiconductor layer is overlying the insulator layer. A first portion of the semiconductor layer has a first thickness. A second portion of the semiconductor layer has a second thickness. The second thickness is larger than the first thickness. The first transistor has a first active region formed from the first portion of the semiconductor layer. The second transistor has a second active region formed from the second portion of the semiconductor layer. The first transistor may be a planar transistor and the second transistor may be a multiple-gate transistor, for example.

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patent: 2002/0011612 (2002-01-01), Hieda
patent: 2005/0017377 (2005-01-01), Joshi et al.
Chau, R., et al., “A 50nm Depleted-Substrate CMOS Transistor (DST),” IEDM, Mar. 2001, pp. 621-624, IEEE.
Shahidi, G.G., “SOI Technology for the GHz Era,” IBM Journal Res. & Dev., Mar./May 2002, pp. 121-131, vol. 46, No. 2/3, International Business Machines Corporation.

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