Methods and circuits for programming addresses of failed...

Details Methods and circuits for programming addresses of failed... Methods and circuits for programming addresses of failed...

2005-09-19

2008-03-04

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S225700

Reexamination Certificate

active

07339843

ABSTRACT:
A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.

REFERENCES:
patent: 6829176 (2004-12-01), Callaway et al.
patent: 2002/0012282 (2002-01-01), Saito et al.
patent: 2003/0213954 (2003-11-01), Fujima
patent: 2004/0136248 (2004-07-01), Kozuka
patent: 2002042494 (2002-02-01), None
patent: 1020020058488 (2002-07-01), None

Affiliated with

Also associated with

Rating

Methods and circuits for programming addresses of failed... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and circuits for programming addresses of failed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and circuits for programming addresses of failed... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3968986