Methods and circuits for balancing bitline precharge

Details Methods and circuits for balancing bitline precharge Methods and circuits for balancing bitline precharge

2005-09-06

2005-09-06

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000, C365S230040

Reexamination Certificate

active

06940771

ABSTRACT:
A memory array design is provided. Memory cells are defined an intersections of rows and columns. A pair of bitline segments are defined for each column. A connecting load device of each memory cell is connected to either a first or a second of the pair of bitline segments. An equal number of load devices in each column couple to each of the pair of bitlines.

REFERENCES:
patent: 5517451 (1996-05-01), Okuzawa
patent: 5719814 (1998-02-01), Ishikawa
patent: 5850366 (1998-12-01), Coleman, Jr.
patent: 5999480 (1999-12-01), Ong et al.

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