Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-09-01
2003-08-19
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06609222
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory circuits, and more particularly to built-in self test (BIST) circuitry for content addressable memory (CAM) circuits.
2. Description of the Related Art
Modern computer systems and computer networks utilize memory devices for storing data and providing fast access to the data stored therein. A content addressable memory (CAM) is a special type of memory device often used for performing fast destination searches for data stored in the CAM. For example, Internet routers often include a CAM for searching the address of specified data. Thus, the use of CAMs allows routers to perform address searches to facilitate more efficient communication between computer systems over computer networks. Besides routers, CAMs are also utilized in other areas where fast-searches are required such as databases, network adapters, image processing, voice recognition applications, etc.
Conventional CAMs typically include a two-dimensional row and column content addressable memory core array of cells. In such an array, each row typically stores an address, pointer, or bit pattern entry. In a read/write configuration, a CAM may perform “read” and “write” operations at specific addresses as is done in conventional random access memories (RAMs). In another configuration, CAMs unlike RAMs, can perform data “search” operations that simultaneously compare a bit pattern of data against an entire list (i.e., column) of prestored entries (i.e., rows).
As with most memory devices, the conventional CAMs may fail to operate properly due to any number of faults. For example, bit cells of the CAM array may become stuck at some value. Another type of fault occurs when bit cells become electrically coupled during write operations. In such cases, when a specific value is written to one bit cell, the other bit cell in the same row or a different row acquires the same value. Another type of fault is a transition fault, which prevents a bit cell from transitioning from one state into another state. Yet another example is when an address decoding fault occurs, thus causing a wrong cell or cells to be addressed, thereby resulting in the access of data in the wrong location.
Still another type of fault occurs when electrical shorts or other defects cause circuit or memory elements to be stuck-at some value, thereby preventing proper operation of the CAM. Such faults may occur in a CAM itself or its peripheral circuitry. Another fault occurs when CAM circuits operate at a slower speed than expected due to variations in such factors as IC fabrication process, temperature, or voltage. As can be appreciated, such dynamic faults cause undesired delays that can degrade performance of CAM circuits.
To guard against such faults, one approach is to implement a built-in self-test (BIST) technique for detecting some of these types of faults. For example, U.S. Pat. No. 5,107,501 by Yervant Zorian, which is incorporated herein by reference, discloses a BIST technique for testing the data bits in a conventional binary CAM using write and read-match operations. While such method detects faults such as electrical short and open faults and stuck-at faults, it is not well suited for detecting faults in ternary CAMs. Specifically, the bit cells in ternary CAMs are characterized not only by binary states of “0” and “1,” but also by a “don't care” state, which denotes that the state of the associated bit cell is not relevant to a particular CAM search. Consequently, not all functional aspects of a ternary CAM can be tested using the teachings of Zorian.
Also, Zorian can only perform writes to set up searches when search operations are not being performed. Consequently, there will be cases in which BIST searching cannot be performed for several cycles until write operations are complete. This, of course, slows down BIST testing and does not allow the BIST testing to be at the functional speed. Furthermore, the BIST technique described by Zorian tests the CAM rows simultaneously. This technique triggers matches in all rows of the CAM and results in very high power consumption. In essence, the Zorian design is impractical for today's larger CAM implementations. Practical CAM devices with large storage capacities are designed to be used only in a manner that does not cause matches in more than some limited number of rows simultaneously.
In view of the foregoing, what is needed is a method for BIST testing of CAM circuitry and associated BIST testing circuitry.
SUMMARY OF THE INVENTION
The present invention fills this need by providing an architecture for performing built-in self-test (BIST) for CAMS. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core is disclosed. The BIST circuit includes a search port for enabling searches of the CAM core and a maintenance port for enabling addressing of locations of the CAM core. The maintenance port includes writing logic for writing to addresses of the CAM core. The BIST circuit also includes a BIST controller for coordinating BIST testing of the CAM core. The BIST controller is capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core. Thus, the BIST write is capable of being performed in a same cycle as the BIST search.
In another embodiment, a built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core is disclosed. The BIST circuit includes a search port for enabling searches of the CAM core and a maintenance port for enabling addressing of addresses of the CAM core. The maintenance port further includes writing logic for writing to addresses of the CAM core. A BIST controller for coordinating BIST testing of the CAM core is also provided. The BIST controller is capable of performing a BIST search and a BIST write on the CAM core at the same time.
In another embodiment, the search port and maintenance port are distributed and are not part of the BIST controller, so as to reduce the number of global wires required to communicate read/write/search data and results to the CAM core.
In yet another embodiment, content addressable memory (CAM) circuitry with BIST testing capabilities is disclosed. The circuitry includes a plurality of CAM cores and a plurality of BIST circuits that are coupled to each of the CAM cores. A single BIST controller is also included and is capable of controlling BIST testing of each of the plurality of CAM cores. Preferably, the single BIST controller is configured to perform BIST searches on each of the plurality of CAM cores during each cycle and is further configured to perform BIST writing during any cycle including a cycle in which the BIST search occurs.
In still a further embodiment, a method for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core is disclosed. The method includes: (a) writing test data to memory addresses in the CAM core; and (b) searching for test data in the CAM core, the searching being continuously performed one cycle after another and the writing of the test data capable of being performed in a same cycle as one or more search performed during the searching. In one aspect of this embodiment, the method can further include an operation of selecting one row of the CAM core to be valid during the searching, such that matches only occur in the one row in one of the cycles. This aspect enables low power BIST testing.
The advantages of the present invention are numerous. Most notably, the BIST testing architecture enables testing of a CAM core separate from the testing of priority encoders (PEs). In one embodiment, separately testing the CAM core is configured to further enable the testing of one row of the CAM core at
Gibson G. F. Randall
Gupta Sanjay
Chase Shelly A
De'cady Albert
Martine & Penilla LLP
SiberCore Technologies, Inc.
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