Methods and arrangements to manage on-chip memory to reduce...

Details Methods and arrangements to manage on-chip memory to reduce... Methods and arrangements to manage on-chip memory to reduce...

2011-04-26

2011-04-26

Thai, Tuan V. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S100000, C711S154000, C710S005000

Reexamination Certificate

active

07934061

ABSTRACT:
Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

REFERENCES:
patent: 5438670 (1995-08-01), Baror et al.
patent: 6105119 (2000-08-01), Kerr et al.
patent: 6738864 (2004-05-01), Chauvel
patent: 7177985 (2007-02-01), Diefendorff
patent: 2003/0154349 (2003-08-01), Berg et al.
patent: 2004/0103408 (2004-05-01), Chilimbi et al.
patent: 2004/0236922 (2004-11-01), Boucher et al.
patent: 2005/0114559 (2005-05-01), Miller
patent: 2005/0144337 (2005-06-01), Kahle
patent: 2005/0198439 (2005-09-01), Lange et al.
patent: 2006/0085602 (2006-04-01), Huggahalli et al.
patent: 2006/0143513 (2006-06-01), Hillman et al.
Stenström, Per et al., “Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures,” Proceedings of the 19thAnnual International Symposium on Computer Architecture, ACM Press, 1992, pp. 80-91.
Tomkins, Andrew et al., “Informed Multi—Process Prefetching and Caching,” Proceedings of the 1997 ACM Sigmetrics, International Conference on Measurement and Modeling of Computer Systems, ACM Press, 1997, pp. 100-114.
Kimbrel, Tracy et al., “A Trace-Driven Comparison of Algorithms for Parallel Prefetching and Caching,” Proceedings of the 1996 Symposium on Operating Systems Design and Implementation, 1996, pp. 19-34.
“Porting x86 Linux Device Drivers to AMD64 Technology,” Advanced Micro Devices Inc., Last Updated Mar. 11, 2004; Accessed Oct. 4, 2006; http://www.amd.com/us-en/assets/content—type/DownloadedableAssests/Porting—x86—Linux—device—drivers—to—AMD64—Technology.htm., pp. 1-4.
Coady, Yvonne et al., “Using AspectC to Improve the Modularity of Path-Specific Customization in Operating System Code,” Joint 8 European Software Engineering Conference(ESEC) and 9 ACM SIGSOFT Symposium on the Foundations of Software Engineering (FSE), Vienna, Austria, 2001, pp. 88-98.

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