Methods and arrangements for improved spacer formation within a

Details Methods and arrangements for improved spacer formation within a Methods and arrangements for improved spacer formation within a

1997-12-18

2000-08-15

Utech, Benjamin L.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438706, 438199FOR, H01L 2100, H01L 213065

Patent

active

061036110

ABSTRACT:
Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

REFERENCES:
patent: 5751035 (1998-05-01), Kameda et al.
patent: 5770498 (1998-06-01), Becker
patent: 5899722 (1999-05-01), Huang

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