Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-12-18
2001-07-10
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000
Reexamination Certificate
active
06258669
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and apparatus associated with non-volatile memory semiconductor devices.
BACKGROUND ART
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell
8
is depicted in
FIG. 1
a.
As shown, memory cell
8
is viewed in a cross-section through the bit line. Memory cell
8
includes a doped substrate
12
having a top surface
11
, and within which a source
13
a
and a drain
13
b
have been formed by selectively doping regions of substrate
12
. A tunnel oxide
15
separates a floating gate
16
from substrate
12
. An interpoly dielectric
24
separates floating gate
16
from a control gate
26
. Floating gate
16
and control gate
26
are each electrically conductive and typically formed of polysilicon.
On top of control gate
26
there is a silicide layer
28
, which acts to increase the electrical conductivity of control gate
26
. Silicide layer
28
is typically a tungsten silicide (e.g., WSi
2
), that is formed on top of control gate
26
prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell
8
can be programmed, for example, by applying an appropriate programming voltage to control gate
26
. Similarly, memory cell
8
can be erased, for example, by applying an appropriate erasure voltage to source
13
a.
When programmed, floating gate
16
will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate
16
can be programmed to a binary 1 by applying a programming voltage to control gate
26
, which causes an electrical charge to build up on floating gate
16
. If floating gate does not contain a threshold level of electrical charge, then floating gate
16
represents a binary 0. During erasure, the charge is removed from floating gate
16
by way of the erasure voltage applied to source
13
a.
FIG. 1
b
depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line. In
FIG. 1
b,
the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate
12
. For example,
FIG. 1
b
shows a portion of a floating gate
16
a
associated with a first memory cell, a floating gate
16
b
associated with a second memory cell, and a floating gate
16
c
associated with a third memory cell. Floating gate
16
a
is physically separated and electrically isolated from floating gate
16
b
by a field oxide (FOX)
14
a.
Floating gate
16
b
is separated from floating gate
16
c
by a field oxide
14
b.
Floating gates
16
a,
16
b,
and
16
c
are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate
12
, tunnel oxide
15
, and field oxides
14
a-b.
Interpoly dielectric layer
24
has been conformally deposited over the exposed portions of floating gates
16
a-c
and field oxide regions
14
a-b.
Interpoly dielectric layer
24
isolates floating gates
16
a-c
from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate
26
. Interpoly dielectric layer
24
typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as a oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the features depicted in the memory cells of
FIGS. 1
a-b,
places a burden on the fabrication process to deposit/form the floating gate
16
and control gate
26
without creating deleterious effects within the memory cell. Of particular concern caused by the shrinking dimensions is the need to provide adequate isolation between each of the floating gates
16
a-c,
and between each of the floating gates
16
a-c
and control gate
26
, while also providing an adequately arranged floating/control gate configuration.
SUMMARY OF THE INVENTION
These needs and others are met by the present invention, which provides methods and arrangements that increase the process control during the fabrication of semiconductor devices, and in particular, during the formation of the floating/control gate configuration in a non-volatile memory semiconductor device. In accordance with one aspect of the present invention, it has been found that, in certain semiconductor arrangements, the topology created by the space between adjacent floating gates (e.g.,
16
a
and
16
b,
can be so severe in shape (e.g., deep and narrow) that the silicide layer
28
formed on the overlying control gate
26
often contains significant depressions over the space. These significant depressions can lead to cracks in the silicide layer
28
during subsequent thermal processing of the semiconductor device, which tends to stress the silicide layer
28
.
In accordance with one aspect of the present invention, the amount and shape of the open spaces located between floating gates following patterning is reduced and altered to present a modified topology that is not so severe. The modified topology improves the step coverage of both the control gate material and silicide material, and thereby does not cause significant depressions to form in the subsequently formed silicide layer
28
. Consequently, cracking of silicide layer
28
is substantially less likely to occur during the subsequent thermal processes.
Thus, in accordance with certain embodiments of the present invention, a method, and an associated arrangement, are provided. The method includes the step of forming at least two isolating regions, separated by an isolated region, within a substrate. The method further includes the steps of forming a tunnel oxide on the top surface of the substrate and within the isolated region, forming a floating gate over the substrate, forming a dielectric layer on the floating gate and at least a portion of each of the two isolating regions, and forming at least one spacer on a portion of the dielectric layer, wherein the portion of the dielectric layer is at least partially located directly over and contacting one of the two isolating regions.
The above stated needs are further met by still other embodiments of the present invention that also include a method and associated arrangements. The method for fabricating a semiconductor device includes the step of forming at least two isolating regions, separated by an isolated region, within a substrate. The method further includes the steps of forming a floating gate over the substrate, forming at least one spacer that contacts the floating gate and one of the two isolating regions, and forming a dielectric layer on the floating gate, the spacer and at least a portion of each
Advanced Micro Devices , Inc.
Chaudhuri Olik
Coleman William David
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