Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2003-10-13
2008-08-19
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S718000, C714S723000, C365S200000, C365S201000
Reexamination Certificate
active
07415640
ABSTRACT:
Various methods and apparatuses are described in which a repair data container may store a concatenated repair signature for multiple memories having one or more redundant components associated with each memory. A processor contains redundancy allocation logic to execute one or more repair algorithms to generate a repair signature for each memory. The repair data container may store actual repair signatures for each memory having one or more defective memory cells detected during fault testing and dummy repair signatures for each memory with no defective memory cells. The processor may contain logic configured to compress an amount of bits making up the concatenated repair signature, to decompress the amount of bits making up the concatenated repair signature, and to compose the concatenated repair signature for all of the memories sharing the repair data container. The repair data container may have an amount of fuses to store the actual repair signatures for an adjustable subset of the multiple memories.
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Darbinyan Karen
Torjyan Gevorg
Zorian Yervant
Britt Cynthia
Nguyen Steve
Rutan & Tucker LLP
Virage Logic Corporation
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